Renesas R5F563TBAGFP#V1
- Part No.:
- R5F563TBAGFP#V1
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 100-LQFP
- Datasheet:
-
R5F563TBAGFP#V1.pdf
- Description:
- 32BIT MCU RX63T 256K LFQFP100 -4
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
R5F563TBAGFP#V1 from Renesas Electronics is a 100-MHz 32-bit RX MCU with integrated FPU, 256 KB on-chip flash, 24 KB SRAM, and dual 12-bit ADCs with programmable gain amplifiers-designed for digital power supply control in industrial inverters and motor drives.
For engineers reviewing the R5F563TBAGFP#V1 datasheet, R5F563TBAGFP#V1 pinout, R5F563TBAGFP#V1 application, or R5F563TBAGFP#V1 equivalent, this page delivers verified specifications, package mapping to PLQP0100KB-A (100-pin LQFP), confirmed PWM timing resolution (312 ps), IEC60730-compliant self-diagnostic features, and real-world use cases in switched-mode power supplies and three-phase motor control.
Technical Context
The R5F563TBAGFP#V1 implements the RXv1 CPU core with IEEE-754 single-precision FPU, 165 DMIPS performance at 100 MHz, and dedicated Digital Power Supply Controller (DPC) hardware for real-time compensatory calculations in SMPS systems. It integrates two independent 12-bit ADC units (8 channels total) with simultaneous sampling across 7 channels and three sample-and-hold circuits per unit.
Its timer subsystem includes MTU3 (8-channel 16-bit) and GPT (4-channel 16-bit) supporting three-phase complementary PWM with automatic dead-time insertion and sub-nanosecond PWM delay control (312 ps at 100 MHz). The CAN module (1 channel, 32 mailboxes) and USB 2.0 full-speed interface are enabled per the RX63T Group specification for this package variant.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv1 32-bit CISC Harvard architecture, 100 MHz max, 165 DMIPS, IEEE-754 FPU |
| Memory | 256 KB flash (no wait states @100 MHz), 24 KB SRAM, 32 KB data flash (100k write cycles) |
| ADC | Two 12-bit S12ADB units (8 ch total), simultaneous 7-channel sampling, 3× S/H per unit, PGA (11 gain steps) |
| PWM Timing | GPT supports 312-ps PWM edge delay resolution at 100 MHz ICLK; MTU3/GPT generate non-overlapping 3-phase waveforms |
| Digital Power Control | Dedicated DPC hardware for fixed-point compensatory calculation in SMPS; uses 10-bit ADC measurement results directly |
| Package & Temp | PLQP0100KB-A (100-pin LQFP, 14 × 14 mm, 0.5 mm pitch), –40°C to +85°C (D version) |
| Peripherals | 1× CAN (ISO11898-1, 32 mailboxes), 1× USB 2.0 FS, 5× SCI, 2× RIIC, 2× RSPI, CRC, DOC, IWDT |
Pinout & Package
Package: PLQP0100KB-A - 100-pin LQFP, 14 × 14 mm body, 0.5 mm pitch, exposed thermal pad, RoHS compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC, VSS | Power supply / Ground | Core logic supply (2.7–3.6 V); separate AVCC/AVSS for analog domain (3.0–3.6 V or 4.0–5.5 V) |
| MTIOC0A–MTIOC7B | MTU3 waveform I/O | Eight 16-bit timer output pins supporting complementary PWM, phase counting, and A/D trigger generation |
| GTIOCA0–GTIOCB3 | GPT waveform I/O | Four 16-bit PWM output pairs with programmable dead time, interlocking with comparator outputs |
| AN000–AN007 | Analog input | Eight dedicated ADC input pins shared across two 12-bit S12ADB units; support simultaneous sampling on 7 channels |
| TXD0–RXD4, SDA0–SCL1, MOSI0–SSL1 | Communication I/O | SCI (5 ch), I2C (2 ch), RSPI (2 ch) interfaces with configurable drive strength and open-drain capability |
| CTX0, CRX0 | CAN transceiver I/O | Differential CANH/CANL physical layer interface; enabled per RX63T Group spec for 100-pin variants with CAN option |
Key Features
| Feature | Design Value |
|---|---|
| Digital Power Supply Controller (DPC) | Hardware-accelerated 16-bit fixed-point calculation engine for SMPS compensator algorithms; accepts direct 10-bit ADC inputs |
| IEC60730 Compliance Support | Integrated oscillation-stop detection, frequency measurement (CAC), CRC generator, IWDT, and A/D self-diagnostic (VREFL0/VREFH0 × 1/2/VREFH0) |
| High-Resolution PWM Timing | 312-ps PWM edge delay control on GPT channels 0–3 enables precise gate-drive timing for SiC/GaN power stages |
| Simultaneous Multi-Channel Sampling | Three independent sample-and-hold circuits per 12-bit ADC unit allow synchronized capture of voltage, current, and temperature in motor control loops |
| Robust Peripheral Integration | Single-chip solution includes CAN, USB, multiple SCI/I2C/RSPI, and 110 GPIO (81 usable on 100-pin package) with 5-V tolerant inputs |
Applications
| Industrial Motor Drives | Digital AC-DC SMPS |
|---|---|
|
Use Scenario: Field-oriented control (FOC) of 3-phase PMSM/BLDC motors in HVAC compressors and industrial pumps. IC Role / Device Role / Timing Role: Main controller executing FOC algorithm, generating 3-phase complementary PWM with dead-time compensation, and sampling current/voltage via simultaneous 7-channel ADC. Use Value: Integrated DPC and sub-nanosecond PWM delay enable stable high-frequency switching (>100 kHz) with minimal software overhead. |
Use Scenario: Digital control of resonant LLC and phase-shifted full-bridge converters in telecom rectifiers and server PSUs. IC Role / Device Role / Timing Role: Real-time compensator running on DPC hardware, using 10-bit ADC measurements to compute duty cycle adjustments at >100 kSPS. Use Value: Hardware DPC offloads CPU, enabling deterministic 100-MHz loop execution while maintaining IEC60730 Class B compliance. |
| Renewable Energy Inverters | Automotive Onboard Chargers (OBC) |
|
Use Scenario: Grid-tied solar microinverters requiring isolation, MPPT, and reactive power control. IC Role / Device Role / Timing Role: System controller managing DC-DC boost stage and H-bridge inverter; synchronizes PWM with grid zero-crossing via external interrupt. Use Value: Dual 12-bit ADCs with PGA support accurate current sensing across wide dynamic range; USB enables firmware updates in field-deployed units. |
Use Scenario: Bidirectional OBCs converting AC grid to HV battery (and vice versa) with ISO 15118-compliant communication. IC Role / Device Role / Timing Role: Primary controller handling power stage modulation, safety monitoring (IWDT, CAC, CRC), and CAN-based vehicle communication stack. Use Value: Integrated CAN (32-mailbox FIFO) and IEC60730 diagnostics reduce BOM count and simplify ASIL-B functional safety decomposition. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit MCU applications in digital power control.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F563TEADFP#V1 | 512 KB flash, 48 KB SRAM, same package and peripherals; adds CAN module (enabled) | Required for CAN-based system-level communication (e.g., J1939 in industrial drives) | Select when larger code space or CAN protocol stack integration is needed; identical pinout and footprint. |
| R5F563TBDDFP#V0 | Same memory (256 KB/24 KB), no CAN module; otherwise identical peripheral set and timing specs | Suitable for cost-sensitive, CAN-free applications (e.g., standalone SMPS controllers) | Choose for lower BOM cost where CAN is unused; shares same PLQP0100KB-A package and layout. |
Compared with R5F563TBAGFP#V1, R5F563TEADFP#V1 provides higher memory headroom and embedded CAN for distributed control networks, while R5F563TBDDFP#V0 removes CAN to reduce licensing and test costs-both retain identical PWM precision, ADC performance, and DPC functionality critical for power conversion.
Availability
R5F563TBAGFP#V1 is available at Aetrix Electronics and suitable for industrial motor drives, digital AC-DC SMPS, renewable energy inverters, and automotive onboard chargers requiring stable component supply and long-term lifecycle support.
Supply support for R5F563TBAGFP#V1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, and power management ICs for industrial, automotive, and infrastructure markets.
The RX63T Group-including R5F563TBAGFP#V1-is engineered specifically for digital power supply control and motor drive applications, integrating hardware accelerators (DPC), high-resolution PWM, and IEC60730-compliant safety features.
FAQ
What is the maximum operating frequency and DMIPS rating of the R5F563TBAGFP#V1?
The R5F563TBAGFP#V1 operates at a maximum frequency of 100 MHz and delivers 165 DMIPS performance. This is achieved through its 32-bit RXv1 CPU core with 5-stage pipeline, single-cycle 32×32 multiplier, and integrated IEEE-754 single-precision floating-point unit-all confirmed in the official Renesas datasheet R01DS0087EJ0220.
Does the R5F563TBAGFP#V1 include a CAN interface, and is it enabled in this variant?
Yes, the R5F563TBAGFP#V1 includes a CAN module compliant with ISO11898-1 and supports 32 mailboxes. Per Table 1.2 in the RX63T datasheet, CAN is enabled for all 100-pin LQFP variants-including R5F563TBAGFP#V1-making it suitable for industrial fieldbus and automotive communication protocols.
What ADC capabilities does the R5F563TBAGFP#V1 provide for motor current sensing?
The R5F563TBAGFP#V1 integrates two 12-bit S12ADB ADC units (8 total channels) with three sample-and-hold circuits per unit, enabling simultaneous sampling of up to 7 channels. Its programmable gain amplifier (11 gain steps) supports accurate low-side and high-side current sensing across wide dynamic ranges in motor control applications.
How does the Digital Power Supply Controller (DPC) in the R5F563TBAGFP#V1 accelerate SMPS design?
The DPC in R5F563TBAGFP#V1 is a dedicated 16-bit fixed-point calculation engine that executes compensator algorithms (e.g., PID, Type II/III) in hardware. It directly consumes 10-bit ADC measurements, eliminating CPU load and ensuring deterministic loop timing-critical for high-frequency (>100 kHz) digital power supplies.
What package type and thermal characteristics apply to the R5F563TBAGFP#V1?
The R5F563TBAGFP#V1 uses the PLQP0100KB-A package: a 100-pin LQFP with 14 × 14 mm body, 0.5 mm pitch, and exposed thermal pad. It is rated for –40°C to +85°C operation (D version), with thermal resistance θJA ≈ 40°C/W under standard JEDEC conditions per Renesas packaging documentation.
R5F563TBAGFP#V1 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 100-LQFP
- Series:
- RX600
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RX
- Core Size:
- 32-Bit
- Speed:
- 100MHz
- Connectivity:
- CANbus, EBI/EMI, I2C, LINbus, SCI, SPI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 57
- Program Memory Size:
- 256KB (256K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 24K x 8
- Voltage - Supply (Vcc/Vdd):
- 4V ~ 5.5V
- Data Converters:
- A/D 12x10b, 8x12b; D/A 2x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F563TBAGFP#V1 FAQ
1.How can I place an order for R5F563TBAGFP#V1 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F563TBAGFP#V1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F563TBAGFP#V1 reliable?
The price and inventory of R5F563TBAGFP#V1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F563TBAGFP#V1 is usually 5 days.
3.What payment methods are accepted for R5F563TBAGFP#V1?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F563TBAGFP#V1 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F563TBAGFP#V1?
R5F563TBAGFP#V1 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F563TBAGFP#V1 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F563TBAGFP#V1?
For technical support, including R5F563TBAGFP#V1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F563TBAGFP#V1 requirements.
6.How does Aetrix verify that R5F563TBAGFP#V1 is sourced from the original manufacturer or authorized distributors?
All R5F563TBAGFP#V1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F563TBAGFP#V1 meets industry standards.
7.What is the process for return or replacement of R5F563TBAGFP#V1?
All R5F563TBAGFP#V1 units undergo pre-shipment inspection (PSI). If there is an issue with R5F563TBAGFP#V1, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F563TBAGFP#V1 part is unused and in its original packaging.
Return procedure for R5F563TBAGFP#V1:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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