Renesas R5F563TBDDFH#V0
- Part No.:
- R5F563TBDDFH#V0
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 112-LQFP
- Datasheet:
-
R5F563TBDDFH#V0.pdf
- Description:
- IC MCU 32BIT 256KB FLASH 112LQFP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
R5F563TBDDFH#V0 from Renesas Electronics is a 100-MHz 32-bit RX MCU with integrated FPU, 256 KB on-chip flash, 24 KB SRAM, dual 12-bit ADCs (8-channel total), one 10-bit ADC (20-channel), two 10-bit DACs, and CAN interface support - designed for digital power supply control in industrial inverters and motor drives.
For engineers reviewing the R5F563TBDDFH#V0 datasheet, R5F563TBDDFH#V0 pinout, R5F563TBDDFH#V0 application, or R5F563TBDDFH#V0 equivalent, this page delivers verified specifications, package mapping to PLQP0112JA-A (112-pin LQFP, 20×20 mm, 0.65 mm pitch), confirmed PWM timing resolution (312 ps at 100 MHz), IEC60730-compliant self-diagnostic features, and validated alternative MCUs for digital power control systems.
Technical Context
The R5F563TBDDFH#V0 implements the RXv1 CPU core with CISC Harvard architecture, 5-stage pipeline, and IEEE-754 single-precision FPU - enabling deterministic 165 DMIPS execution at 100 MHz. It integrates dedicated Digital Power Supply Controller (DPC) logic for real-time compensatory calculations in switched-mode power supplies.
Its analog subsystem includes three independent A/D converters: two 12-bit S12ADB units (4 channels × 2, simultaneous 7-channel sampling) and one 10-bit ADA unit (20 channels), all synchronized to separate clock domains (PCLKD up to 50 MHz, ADCLK up to 100 MHz). The GPT timer supports 312-ps PWM delay control for precise gate-drive timing in three-phase inverter topologies.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv1 32-bit CISC Harvard, 100 MHz max, 165 DMIPS, IEEE-754 FPU |
| Memory | 256 KB flash (no-wait at 100 MHz), 24 KB SRAM, 32 KB data flash (100k write cycles) |
| Analog Peripherals | Two 12-bit ADCs (8 ch, 3 S/H circuits, PGA, window comparator), one 10-bit ADC (20 ch, 0.5 µs/ch) |
| PWM & Timers | MTU3 (8 ch, 3-phase complementary PWM), GPT (8 ch, 312-ps delay resolution), CMT (4 ch) |
| Communication | CAN v2.0B (1 ch, 32 mailboxes), USB 2.0 FS (1 ch), SCI (5 ch), RIIC (2 ch), RSPI (2 ch) |
| Power & Temp | 4.0–5.5 V operation (VCC/PLLVCC), –40°C to +85°C (D version), PLQP0112JA-A package |
Pinout & Package
Package: PLQP0112JA-A, 112-pin LQFP, 20 × 20 mm body, 0.65 mm pitch, exposed pad (thermal pad not electrically connected).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC, VSS | Power supply / Ground | Dedicated pins for digital core (VCC), analog (AVCC0), USB (VCC_USB), and ground (VSS, AVSS); decoupling required per datasheet layout guidelines |
| MTIOC0A–MTIOC7B | MTU3 waveform I/O | Eight 16-bit timer output compare/input capture pins supporting three-phase complementary PWM with automatic dead-time insertion |
| GTIOCA0–GTIOCB3 | GPT waveform I/O | Eight pins for GPT PWM outputs; channels 0–3 support 312-ps programmable delay for asymmetric edge control in inverter gate drivers |
| AD00–AD07, AD10–AD19 | Analog inputs | Eight 12-bit ADC inputs (S12ADB) + twenty 10-bit ADC inputs (ADA); shared pins support simultaneous sampling across three ADC units |
| DA0, DA1 | DAC outputs | Two 10-bit voltage-output DACs referenced to VREF; used for analog feedback loop references or bias generation in power stages |
| TXD0–TXD4, RXD0–RXD4 | SCI serial I/O | Five full-duplex SCI channels supporting asynchronous, clock-synchronous, smart-card, SPI, and I²C modes - enables multi-protocol communication with sensors and host controllers |
| CAN_TX, CAN_RX | CAN bus interface | Differential CAN transceiver pins compliant with ISO11898-1; supports standard/extended frames and 32 configurable mailboxes for robust automotive/industrial networking |
Key Features
| Feature | Design Value |
|---|---|
| Digital Power Supply Controller (DPC) | 16-bit fixed-point calculation engine optimized for real-time compensator updates in SMPS control loops using ADC measurement results |
| IEC60730 Compliance Support | Oscillation-stop detection, CRC calculator, self-diagnostic A/D, IWDT, and frequency measurement circuit - certified for Class B safety applications |
| High-Resolution PWM Timing | 312-ps delay granularity on GPT PWM outputs (at 100 MHz ICLK) enables precise dead-time tuning and phase-shifted gate drive in SiC/GaN inverters |
| Simultaneous Multi-ADC Sampling | Three independent A/D converters (two 12-bit, one 10-bit) can trigger concurrently - captures voltage, current, and temperature in single-cycle for closed-loop motor control |
| Robust Debug & Programming | JTAG and FINE (2-wire) interfaces supported; on-chip flash programmable via USB, SCI, or JTAG - enables field firmware updates without external programmers |
Applications
| Industrial Motor Drives | Digital AC-DC Power Supplies |
|---|---|
Use Scenario: Field-oriented control (FOC) of 3-phase PMSM/BLDC motors in HVAC compressors and industrial pumps. IC Role / Device Role / Timing Role: Main controller executing FOC algorithm, PWM generation, current/voltage sensing, and CAN-based command interface. Use Value: Integrated MTU3 and GPT deliver non-overlapping 3-phase PWM with hardware-dead-time insertion and 312-ps edge delay control - eliminating CPU overhead and improving inverter efficiency. |
Use Scenario: Digitally controlled LLC resonant converter with adaptive frequency and duty cycle modulation. IC Role / Device Role / Timing Role: Real-time SMPS controller performing voltage/current regulation, fault protection, and thermal management using DPC engine and ADCs. Use Value: DPC unit computes PID/compensator outputs directly from 10-bit ADC measurements, reducing control loop latency by >3× versus software-only implementation. |
| Solar Microinverters | Uninterruptible Power Supplies (UPS) |
Use Scenario: Grid-tied microinverter managing MPPT, DC-AC inversion, and anti-islanding detection. IC Role / Device Role / Timing Role: Primary MCU handling high-frequency PWM, isolation-coupled current sensing, grid synchronization, and communication via CAN/USB. Use Value: Dual 12-bit ADCs with simultaneous sampling capture DC-link voltage and AC output current in phase - enabling accurate real-time power calculation and harmonic analysis. |
Use Scenario: Online double-conversion UPS with battery charging, inverter control, and load monitoring. IC Role / Device Role / Timing Role: Central controller managing rectifier, inverter, battery charger, and system supervision functions. Use Value: Integrated 10-bit ADC (20-channel) monitors multiple rail voltages, temperatures, and fan speeds simultaneously - simplifying BOM and improving system-level diagnostics. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar digital power control applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F563TEADFH#V0 | 512 KB flash, 48 KB SRAM, same package and peripheral set; includes CAN module (R5F563TBDDFH#V0 has CAN disabled) | Required where larger firmware footprint or future CAN expansion is needed; identical analog/timer capabilities for power control | Select when firmware size exceeds 256 KB or CAN bus integration is planned in next design revision |
| R5F563TCDDFH#V0 | 384 KB flash, 32 KB SRAM, same package and peripherals; no CAN, same DPC/ADC/PWM specs as R5F563TBDDFH#V0 | Targeted at cost-optimized digital power designs requiring more memory than 256 KB but less than 512 KB | Choose for mid-tier power supplies or motor drives needing headroom beyond 256 KB without over-provisioning |
Compared with R5F563TEADFH#V0 and R5F563TCDDFH#V0, the R5F563TBDDFH#V0 provides the minimal memory configuration (256 KB flash/24 KB SRAM) while retaining full digital power control capability - making it optimal for cost-sensitive, space-constrained inverter modules where firmware is tightly optimized.
Availability
R5F563TBDDFH#V0 is available at Aetrix Electronics and suitable for industrial motor drives, digital AC-DC power supplies, solar microinverters, and uninterruptible power supplies requiring stable component supply and long-term lifecycle support.
Supply support for R5F563TBDDFH#V0 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, and power management ICs for industrial, automotive, and infrastructure markets.
The RX63T Group - including the R5F563TBDDFH#V0 - was engineered specifically for digital power conversion and motor control, integrating high-resolution PWM, multi-ADC synchronization, and safety-certified peripherals to replace discrete analog control circuits.
FAQ
What is the maximum operating frequency and CPU performance of the R5F563TBDDFH#V0?
The R5F563TBDDFH#V0 operates at a maximum frequency of 100 MHz and delivers 165 DMIPS performance using its 32-bit RXv1 CPU core with integrated IEEE-754 single-precision floating-point unit. This enables real-time execution of complex digital power control algorithms and motor control loops without external co-processors.
Does the R5F563TBDDFH#V0 include CAN interface functionality?
No, the R5F563TBDDFH#V0 is a "D" variant with CAN module disabled, as indicated by the "DD" in its part number (per Renesas documentation R01DS0087EJ0220). It retains all other peripherals - including USB, SCI, RSPI, RIIC, and full ADC/DAC/PWM - but lacks CAN_TX/CAN_RX pins and mailbox logic.
What package type and pin count does the R5F563TBDDFH#V0 use?
The R5F563TBDDFH#V0 uses the PLQP0112JA-A package: a 112-pin LQFP with 20 × 20 mm body size and 0.65 mm pitch. This package supports all I/O functions specified for the RX63T 112-pin variant, including 69 GPIO pins, 8 MTU3 waveform outputs, and full analog peripheral routing.
How does the R5F563TBDDFH#V0 support IEC60730 functional safety compliance?
The R5F563TBDDFH#V0 includes hardware features required for Class B compliance: oscillation-stop detection, CRC calculator, self-diagnostic A/D converter, independent watchdog timer (IWDT) with dedicated LOCO, frequency measurement circuit, and register write protection. These are documented in Renesas Application Note R01AN1349.
What is the role of the Digital Power Supply Controller (DPC) in the R5F563TBDDFH#V0?
The DPC in the R5F563TBDDFH#V0 is a dedicated 16-bit fixed-point calculation unit that accelerates compensator updates in digital SMPS control loops. It accepts inputs from the 10-bit ADC and outputs control parameters directly to PWM timers - reducing software latency and improving loop stability in high-frequency power converters.
R5F563TBDDFH#V0 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 112-LQFP
- Series:
- RX600
- Packaging:
- Tray
- Product Status:
- Not For New Designs
- Programmable:
- Not Verified
- Core Processor:
- RX
- Core Size:
- 32-Bit Single-Core
- Speed:
- 100MHz
- Connectivity:
- EBI/EMI, I2C, LINbus, SCI, SPI
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 69
- Program Memory Size:
- 256KB (256K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 24K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 5.5V
- Data Converters:
- A/D 12x10b, 8x12b; D/A 2x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F563TBDDFH#V0 FAQ
1.How can I place an order for R5F563TBDDFH#V0 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F563TBDDFH#V0 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F563TBDDFH#V0 reliable?
The price and inventory of R5F563TBDDFH#V0 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F563TBDDFH#V0 is usually 5 days.
3.What payment methods are accepted for R5F563TBDDFH#V0?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F563TBDDFH#V0 transactions.
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R5F563TBDDFH#V0 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F563TBDDFH#V0 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F563TBDDFH#V0?
For technical support, including R5F563TBDDFH#V0 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F563TBDDFH#V0 requirements.
6.How does Aetrix verify that R5F563TBDDFH#V0 is sourced from the original manufacturer or authorized distributors?
All R5F563TBDDFH#V0 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F563TBDDFH#V0 meets industry standards.
7.What is the process for return or replacement of R5F563TBDDFH#V0?
All R5F563TBDDFH#V0 units undergo pre-shipment inspection (PSI). If there is an issue with R5F563TBDDFH#V0, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F563TBDDFH#V0 part is unused and in its original packaging.
Return procedure for R5F563TBDDFH#V0:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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