Renesas R5F563TCBDFP#V0
- Part No.:
- R5F563TCBDFP#V0
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 100-LQFP
- Datasheet:
-
R5F563TCBDFP#V0.pdf
- Description:
- IC MCU 32BIT 384KB FLASH 100LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:4,592
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
R5F563TCBDFP#V0 from Renesas Electronics is a 100-MHz 32-bit RX CPU-based microcontroller with integrated FPU, 384 KB on-chip flash, 32 KB SRAM, dual 12-bit ADCs (with programmable gain amplifiers and window comparators), one 10-bit 20-channel ADC, two 10-bit DACs, CAN 2.0B interface, USB 2.0 full-speed, and hardware digital power supply controller (DPC) - designed for real-time motor control and digital power conversion in industrial inverters.
For engineers reviewing the R5F563TCBDFP#V0 datasheet, R5F563TCBDFP#V0 pinout, R5F563TCBDFP#V0 application, or R5F563TCBDFP#V0 equivalent, this MCU delivers deterministic PWM timing (312-ps resolution), simultaneous 7-channel ADC sampling, IEC60730-compliant self-test features, and dedicated hardware acceleration for switched-mode power supply control loops - critical for high-reliability embedded power systems.
Technical Context
The R5F563TCBDFP#V0 implements the RXv1 CPU core with CISC Harvard architecture, 5-stage pipeline, and IEEE-754 single-precision FPU - enabling 165 DMIPS at 100 MHz. Its clock system integrates PLL, LOCO oscillators, and frequency accuracy measurement (CAC) for robust timing integrity.
It features two complementary PWM timer units: MTU3 (8 channels, 3-phase + single-phase outputs) and GPT (8 channels, with 312-ps PWM delay control), both synchronized to PCLKA at 100 MHz. The DPC unit performs fixed-point compensator calculations using raw 10-bit ADC inputs - eliminating software overhead in digital power control.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv1 32-bit CISC Harvard, 100 MHz max, 165 DMIPS, IEEE-754 FPU |
| Memory | 384 KB flash (no-wait @100 MHz), 32 KB SRAM, 32 KB data flash (100k erase cycles) |
| ADC System | Dual 12-bit S12ADB (4 ch × 2 units, 3× sample-and-hold, PGA, window comparator); one 10-bit ADA (20 ch, 0.5 µs/ch @100 MHz ADCLK) |
| PWM & Timers | MTU3 (8×16-bit, 3-phase complementary + dead-time auto-gen); GPT (8×16-bit, 312-ps PWM delay resolution); CMT (4×16-bit) |
| Communication | CAN 2.0B (1 channel, 32 mailboxes), USB 2.0 FS (1 port, 2 KB buffer), 5× SCI, 2× RIIC, 2× RSPI |
| Power & Safety | Single 4.0–5.5 V supply, –40°C to +85°C (D version), IEC60730 support (oscillation stop detection, CRC, IWDT, ADC self-diagnostic) |
| Digital Power Control | Dedicated DPC unit with 16-bit fixed-point calculation engine for SMPS compensator math, fed directly by 10-bit ADC results |
Pinout & Package
Package: PLQP0100KB-A, 100-pin LQFP (14 × 14 mm, 0.5 mm pitch), RoHS-compliant, moisture sensitivity level 3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / VSS | Power supply / Ground | Core and I/O supply pins; supports single 4.0–5.5 V operation with separate AVCC/AVCC0 for analog subsystems |
| XTAL / EXTAL | External crystal oscillator input/output | Supports 4–12.5 MHz crystal for main clock generation; enables high-accuracy timing for motor commutation and power regulation |
| MTIOC0A–D / GPTIO0–7 | PWM waveform output pins | Hardware-driven complementary PWM outputs with automatic dead-time insertion and phase-shift capability - offloads CPU during inverter gate driving |
| AD00–AD19 | Analog input channels | 20 dedicated 10-bit ADC inputs (ADA unit); plus 8 additional 12-bit inputs (S12ADB) with programmable gain and window comparison |
| CAN_TX / CAN_RX | CAN bus transceiver interface | Dedicated differential pair supporting ISO 11898-1 compliant communication at up to 1 Mbps - used for system-level monitoring and configuration in power modules |
Key Features
| Feature | Design Value |
|---|---|
| 312-ps PWM timing resolution | Enables precise dead-time control and phase alignment in high-frequency SiC/GaN inverter designs without CPU intervention |
| Simultaneous 7-channel ADC sampling | Allows synchronized acquisition of DC-link voltage, phase currents, and temperature sensors - essential for vector control and protection algorithms |
| Dedicated Digital Power Controller (DPC) | Hardware-accelerated 16-bit fixed-point compensator math using raw ADC data - reduces loop latency to <1 µs in closed-loop SMPS control |
| IEC60730 Class B compliance support | Integrated features include oscillation-stop detection, CRC calculator, independent watchdog (IWDT), and ADC self-diagnostic - simplifies functional safety certification |
| Three-phase inverter PWM engine | MTU3 provides two independent 3-phase complementary PWM outputs with automatic dead-time generation and fault-triggered pin disable (POE3) |
Applications
| Industrial Motor Inverters | Digital AC/DC Power Supplies |
|---|---|
|
Use Scenario: Closed-loop field-oriented control (FOC) of 3-phase PMSM/BLDC motors in HVAC compressors and industrial drives. IC Role / Device Role / Timing Role: Real-time execution of FOC algorithm, generation of synchronized 3-phase PWM waveforms with sub-nanosecond timing precision, and simultaneous sampling of current/voltage feedback. Use Value: Eliminates need for external FPGA or DSP co-processor; enables single-chip solution with deterministic 100-MHz interrupt response and hardware-accelerated trigonometric math via FPU. |
Use Scenario: Digital control of resonant LLC and phase-shifted full-bridge converters in telecom rectifiers and server PSUs. IC Role / Device Role / Timing Role: Execution of PID/compensator algorithms in DPC unit, real-time ADC sampling of output voltage/current, and generation of adaptive PWM with 312-ps edge placement. Use Value: Reduces control loop latency to under 1 µs; supports dynamic load transient response <10 µs and eliminates software-based compensator bottlenecks. |
| Uninterruptible Power Systems (UPS) | Renewable Energy Inverters |
|
Use Scenario: Dual-role control of battery charging and AC line-interactive inverter in online UPS systems. IC Role / Device Role / Timing Role: Simultaneous management of buck charger control and 3-phase inverter output, with seamless transfer logic and harmonic compensation using FPU-accelerated FFT. Use Value: Single R5F563TCBDFP#V0 handles both grid-tie and battery-isolated modes; integrated CAN enables communication with BMS and upstream SCADA systems. |
Use Scenario: Grid-synchronized solar string inverters requiring anti-islanding detection and reactive power injection. IC Role / Device Role / Timing Role: High-accuracy grid synchronization via hardware PLL, real-time harmonic analysis using FPU, and adaptive reactive power control via 10-bit DAC outputs. Use Value: Meets IEEE 1547-2018 requirements for voltage/frequency ride-through and reactive power response with <20-ms latency. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar motor and power control applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F563TEBDFP#V0 | 512 KB flash, 48 KB SRAM, same package and peripheral set; includes USB 2.0 FS and CAN | Required for firmware-over-the-air (FOTA) updates and larger control algorithms; higher memory headroom for dual-core emulation or safety partitioning | Select when >384 KB code space needed or when USB-based field programming is mandatory |
| R5F563TCDDFP#V0 | Same flash/SRAM size and package, but excludes CAN module; retains all ADC, PWM, DPC, and USB functionality | Suitable for standalone power modules where CAN is unnecessary; lower cost and reduced EMI footprint | Select for cost-sensitive, isolated power converter designs without system-level bus communication |
Compared with R5F563TCBDFP#V0, R5F563TEBDFP#V0 offers greater memory for complex control stacks and diagnostics, while R5F563TCDDFP#V0 removes CAN to reduce BOM cost and simplify layout - both retain identical PWM timing, ADC performance, and DPC acceleration critical for digital power design.
Availability
R5F563TCBDFP#V0 is available at Aetrix Electronics and suitable for industrial motor drives, digital AC/DC power supplies, uninterruptible power systems, and renewable energy inverters requiring stable component supply across extended product lifecycles.
Supply support for R5F563TCBDFP#V0 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, and power management solutions for automotive, industrial, and IoT markets.
The RX63T Group - including R5F563TCBDFP#V0 - was engineered specifically for real-time digital power conversion and motor control, integrating hardware accelerators (DPC, high-resolution PWM, simultaneous ADC) to replace discrete DSP+FPGA architectures.
FAQ
What is the maximum operating frequency and CPU performance of the R5F563TCBDFP#V0?
The R5F563TCBDFP#V0 operates at a maximum frequency of 100 MHz and delivers 165 DMIPS using its 32-bit RXv1 CPU core with integrated IEEE-754 single-precision floating-point unit. This performance level enables real-time execution of field-oriented control (FOC) algorithms and digital power supply compensators without external coprocessors.
Does the R5F563TCBDFP#V0 include CAN interface support?
Yes, the R5F563TCBDFP#V0 includes a fully compliant ISO 11898-1 CAN 2.0B module with 32 configurable mailboxes, supporting bit rates up to 1 Mbps. This interface is factory-enabled and used for system-level communication in motor drive and UPS applications.
What ADC resources are available on the R5F563TCBDFP#V0?
The R5F563TCBDFP#V0 integrates three ADC subsystems: two independent 12-bit S12ADB units (4 channels each, with sample-and-hold, PGA, and window comparators) and one 10-bit ADA unit with 20 channels and 0.5 µs conversion time at 100 MHz ADCLK - enabling simultaneous sampling across 7 channels.
How does the Digital Power Controller (DPC) in the R5F563TCBDFP#V0 function?
The DPC in the R5F563TCBDFP#V0 is a dedicated hardware accelerator that performs 16-bit fixed-point compensator calculations (e.g., PID, lead-lag) using raw 10-bit ADC inputs. It operates autonomously from the CPU, reducing closed-loop latency to under 1 µs - critical for high-frequency GaN/SiC power stages.
What package type and pin count does the R5F563TCBDFP#V0 use?
The R5F563TCBDFP#V0 uses the PLQP0100KB-A package: a 100-pin LQFP measuring 14 × 14 mm with 0.5 mm pitch. This package provides 57 GPIO pins, including 16 open-drain outputs, and supports industrial temperature range (–40°C to +85°C).
R5F563TCBDFP#V0 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 100-LQFP
- Series:
- RX600
- Packaging:
- Tray
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Core Processor:
- RX
- Core Size:
- 32-Bit Single-Core
- Speed:
- 100MHz
- Connectivity:
- CANbus, EBI/EMI, I2C, LINbus, SCI, SPI, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 57
- Program Memory Size:
- 384KB (384K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 32K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 12x10b, 8x12b; D/A 2x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F563TCBDFP#V0 FAQ
1.How can I place an order for R5F563TCBDFP#V0 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F563TCBDFP#V0 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F563TCBDFP#V0 reliable?
The price and inventory of R5F563TCBDFP#V0 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F563TCBDFP#V0 is usually 5 days.
3.What payment methods are accepted for R5F563TCBDFP#V0?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F563TCBDFP#V0 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F563TCBDFP#V0?
R5F563TCBDFP#V0 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F563TCBDFP#V0 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F563TCBDFP#V0?
For technical support, including R5F563TCBDFP#V0 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F563TCBDFP#V0 requirements.
6.How does Aetrix verify that R5F563TCBDFP#V0 is sourced from the original manufacturer or authorized distributors?
All R5F563TCBDFP#V0 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F563TCBDFP#V0 meets industry standards.
7.What is the process for return or replacement of R5F563TCBDFP#V0?
All R5F563TCBDFP#V0 units undergo pre-shipment inspection (PSI). If there is an issue with R5F563TCBDFP#V0, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F563TCBDFP#V0 part is unused and in its original packaging.
Return procedure for R5F563TCBDFP#V0:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R5F563TCBDFP#V0 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

