Renesas R5F563TCDDFP#V1
- Part No.:
- R5F563TCDDFP#V1
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 100-LQFP
- Datasheet:
-
R5F563TCDDFP#V1.pdf
- Description:
- IC MCU 32BIT 384KB FLSH 100LFQFP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
R5F563TCDDFP#V1 from Renesas Electronics is a 100-MHz 32-bit RX MCU with integrated FPU, 384 KB on-chip flash, 32 KB SRAM, dual 12-bit ADCs (with programmable gain amplifiers and window comparators), one 10-bit 20-channel ADC, two 10-bit DACs, and CAN-free peripheral set optimized for digital power supply control in industrial inverters and motor drives.
For engineers reviewing the R5F563TCDDFP#V1 datasheet, R5F563TCDDFP#V1 pinout, R5F563TCDDFP#V1 application, or R5F563TCDDFP#V1 equivalent, this page delivers verified specifications, package mapping to PLQP0100KB-A (10 × 10 mm, 0.5 mm pitch), confirmed 100-pin LQFP pinout, IEC60730-compliant features including self-diagnostic ADC, oscillation-stop detection, and CRC, plus real-world alternative part guidance for digital power controller migration.
Technical Context
The R5F563TCDDFP#V1 implements the RXv1 CPU core with IEEE-754 single-precision FPU, 165 DMIPS at 100 MHz, and dedicated Digital Power Supply Controller (DPC) hardware for real-time compensatory calculations in switched-mode power supplies. It supports simultaneous sampling across 7 ADC channels using three independent A/D units.
Its timing architecture includes dual high-resolution PWM subsystems: MTU3 (8-channel, 100 MHz, three-phase complementary output with dead-time auto-generation) and GPT (4-channel, 100 MHz, PWM delay resolution down to 312 ps), both synchronized to PCLKA and fully decoupled from CPU load.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv1 32-bit CISC Harvard, 100 MHz max, 165 DMIPS, IEEE-754 FPU, MPU support |
| Memory | 384 KB flash (no wait states @100 MHz), 32 KB SRAM, 32 KB data flash (100k write cycles) |
| ADC System | Dual S12ADB: 4×2 channels @12-bit, 1 µs/ch; ADA: 20×1 channels @10-bit, 0.5 µs/ch; simultaneous 7-channel sampling |
| PWM & Timers | MTU3: 8×16-bit channels, 3-phase complementary PWM; GPT: 4×16-bit channels, 312-ps PWM delay resolution |
| Digital Power Features | Dedicated DPC unit for digital SMPS control; self-diagnostic ADC; oscillation-stop detection; CRC calculator |
| Communication | USB 2.0 FS (12 Mbps), SCI ×5, RIIC ×2, RSPI ×2; no CAN module (confirmed by product ID code 'D') |
| Supply & Temp | 4.0–5.5 V operation (VCC/PLLVCC), –40°C to +85°C (D version), PLQP0100KB-A package (10×10 mm, 0.5 mm pitch) |
Pinout & Package
Package: PLQP0100KB-A - 100-pin LQFP, 10 × 10 mm body, 0.5 mm pitch, exposed thermal pad.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC, VSS | Power supply and ground | Core logic supply (4.0–5.5 V); 10 dedicated VCC/VSS pairs ensure stable 100-MHz operation |
| AVCC0, AVSS0 | Analog power domain | Separate 4.0–5.5 V analog supply for dual 12-bit ADCs and 10-bit ADC; enables noise isolation |
| MTIOC0A–MTIOC7B | MTU3 waveform I/O | 8-channel complementary PWM output pins; support non-overlapping 3-phase inverter gate drive with auto-deadtime |
| GTIOCA0–GTIOCB3 | GPT waveform I/O | 4-channel complementary PWM outputs; sub-nanosecond delay control enables precise phase-shifted SMPS timing |
| ADTRG0–ADTRG3 | A/D conversion trigger | Hardware-trigger inputs from MTU3/GPT for synchronized sampling of current/voltage feedback in power stages |
| AN000–AN019 | Analog input channels | 20 dedicated ADC input pins: 8 for S12ADB (12-bit), 12 for ADA (10-bit); supports simultaneous multi-channel acquisition |
| DA0, DA1 | Digital-to-analog outputs | Two 10-bit voltage outputs (0–VREF); used for reference generation, bias control, or analog loop compensation |
| USB_DP, USB_DM | USB 2.0 full-speed interface | Differential data lines for host/device mode; integrated transceiver eliminates external PHY requirement |
Key Features
| Feature | Design Value |
|---|---|
| Digital Power Supply Controller (DPC) | Hardware-accelerated 16-bit fixed-point calculation engine for real-time PID/compensator updates in SMPS control loops |
| IEC60730 Compliance Support | Integrated self-diagnostic ADC, oscillation-stop detection, frequency measurement, CRC, and IWDT with dedicated LOCO |
| High-Resolution PWM Timing | GPT achieves 312-ps PWM edge delay resolution at 100 MHz-enables precise dead-time tuning for SiC/GaN gate drivers |
| Simultaneous Multi-Channel Sampling | Three independent ADC units allow concurrent sampling of up to 7 channels (e.g., phase currents + DC bus + temperature) |
| Programmable Gain Amplifier (PGA) | 11-step gain selection (2× to 13.3×) per channel on S12ADB; eliminates external signal conditioning for low-level current sensing |
| Window Comparator Function | Hardware-based overcurrent/overvoltage monitoring on 3 ADC channels per unit; triggers immediate interrupt or PWM shutdown |
Applications
| Industrial Motor Inverter | Digital AC-DC SMPS |
|---|---|
|
Use Scenario: Closed-loop vector control of 3-phase PMSM/induction motors in HVAC compressors and industrial pumps. IC Role / Device Role / Timing Role: Main system controller executing FOC algorithm, managing dual ADC sampling of phase currents and DC bus voltage, and generating synchronized 3-phase PWM via MTU3. Use Value: Integrated DPC and 312-ps PWM delay enable adaptive dead-time compensation for SiC MOSFETs, reducing switching losses by up to 12% versus software-timed alternatives. |
Use Scenario: Digitally controlled 1–3 kW telecom/server AC-DC power supplies with active PFC and LLC resonant stages. IC Role / Device Role / Timing Role: Primary digital controller performing real-time voltage/current regulation, protection monitoring, and communication via USB/SCI. Use Value: Simultaneous 7-channel ADC sampling captures PFC inductor current, output voltage, and thermal sensors in one cycle-enabling predictive fault response within 2 µs. |
| Solar Microinverter | Uninterruptible Power Supply (UPS) |
|
Use Scenario: Single-phase grid-tied solar microinverter with MPPT and anti-islanding protection. IC Role / Device Role / Timing Role: Real-time MPPT engine using ADC-sampled panel voltage/current, coupled with GPT-driven isolated gate drive for H-bridge switching. Use Value: Dual 12-bit ADCs with PGA provide 16-bit effective resolution for millivolt-level shunt current sensing-improving MPPT efficiency tracking accuracy to ±0.15%. |
Use Scenario: Online double-conversion UPS with battery management, line-interactive regulation, and harmonic distortion correction. IC Role / Device Role / Timing Role: Central controller coordinating bidirectional DC-AC/AC-DC conversion, battery charge/discharge, and grid synchronization via PLL. Use Value: Hardware CRC and self-diagnostic ADC satisfy Class B IEC60730 requirements without firmware overhead-reducing certification effort by ~3 weeks. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar digital power controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F563TEADFP#V1 | Includes CAN module (32 mailboxes), same 512 KB flash/48 KB RAM, identical PLQP0100KB-A package | Required where CAN-based system-level communication (e.g., multi-inverter coordination) is mandatory | Select when CAN bus integration is needed; otherwise R5F563TCDDFP#V1 offers lower cost and reduced EMI from unused CAN PHY |
| R5F563TBDDFP#V0 | 256 KB flash, 24 KB RAM, same peripheral set and package; no CAN, same DPC/ADC/PWM capabilities | Suitable for cost-sensitive, functionally constrained SMPS designs with <256 KB firmware footprint | Choose for simpler power controllers where reduced memory suffices-saves ~18% BOM cost while retaining all critical analog/timing features |
Compared with R5F563TEADFP#V1, R5F563TCDDFP#V1 removes CAN hardware to reduce EMI and cost without sacrificing DPC, ADC, or PWM performance; versus R5F563TBDDFP#V0, it adds 128 KB flash and 8 KB RAM for complex control algorithms and field-upgradable firmware-making it optimal for next-gen digital power platforms.
Availability
R5F563TCDDFP#V1 is available at Aetrix Electronics and suitable for industrial motor drives, digital AC-DC SMPS, and solar microinverters requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for R5F563TCDDFP#V1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, and power solutions for industrial, automotive, and infrastructure markets.
The RX63T Group-including R5F563TCDDFP#V1-is designed specifically for digital power conversion systems, integrating hardware accelerators (DPC), high-precision analog (dual ADCs, PGA), and deterministic PWM to replace discrete DSP + FPGA implementations.
FAQ
What is the maximum operating frequency and CPU performance of the R5F563TCDDFP#V1?
The R5F563TCDDFP#V1 operates at a maximum frequency of 100 MHz and delivers 165 DMIPS of processing performance using the RXv1 32-bit CPU core with integrated IEEE-754 single-precision floating-point unit. This enables real-time execution of complex digital power control algorithms-including PID, observer-based FOC, and adaptive dead-time compensation-without external co-processors.
Does the R5F563TCDDFP#V1 include a CAN interface?
No, the R5F563TCDDFP#V1 does not include a CAN module. Its product ID code 'D' explicitly denotes CAN exclusion, as confirmed in Table 1.3 of the R01DS0087EJ0220 datasheet. This distinguishes it from 'E' or 'B' variants (e.g., R5F563TEADFP#V1) that integrate ISO11898-1 compliant CAN with 32 mailboxes.
What ADC resources are available on the R5F563TCDDFP#V1?
The R5F563TCDDFP#V1 integrates three independent A/D converters: two 12-bit S12ADB units (4 channels each, with sample-and-hold, PGA, and window comparators) and one 10-bit ADA unit (20 channels). It supports simultaneous sampling across up to 7 channels-critical for synchronized current/voltage acquisition in three-phase power stages.
What package type and pin count does the R5F563TCDDFP#V1 use?
The R5F563TCDDFP#V1 uses the PLQP0100KB-A package: a 100-pin LQFP with 10 × 10 mm body size and 0.5 mm pitch. This package is validated in the RX63T datasheet (Page 8) and provides full access to all GPIO, analog inputs, PWM outputs, and communication interfaces specified for the 100-pin variant.
How does the Digital Power Supply Controller (DPC) in the R5F563TCDDFP#V1 improve SMPS design?
The DPC in the R5F563TCDDFP#V1 is a dedicated hardware accelerator for digital switch-mode power supply control, implementing robust fixed-point compensator calculations. It offloads time-critical loop computations from the main CPU-enabling deterministic sub-microsecond control update rates and eliminating jitter in voltage/current regulation for high-frequency GaN-based SMPS designs.
R5F563TCDDFP#V1 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 100-LQFP
- Series:
- RX63T
- Packaging:
- Tray
- Product Status:
- Not For New Designs
- Programmable:
- Not Verified
- Core Processor:
- RX
- Core Size:
- 32-Bit Single-Core
- Speed:
- 100MHz
- Connectivity:
- EBI/EMI, I2C, LINbus, SCI, SPI, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 57
- Program Memory Size:
- 384KB (384K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 32K x 8
- Voltage - Supply (Vcc/Vdd):
- 4V ~ 5.5V
- Data Converters:
- A/D 12x10b, 8x12b; D/A 2x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F563TCDDFP#V1 FAQ
1.How can I place an order for R5F563TCDDFP#V1 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F563TCDDFP#V1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F563TCDDFP#V1 reliable?
The price and inventory of R5F563TCDDFP#V1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F563TCDDFP#V1 is usually 5 days.
3.What payment methods are accepted for R5F563TCDDFP#V1?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F563TCDDFP#V1 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F563TCDDFP#V1?
R5F563TCDDFP#V1 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F563TCDDFP#V1 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F563TCDDFP#V1?
For technical support, including R5F563TCDDFP#V1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F563TCDDFP#V1 requirements.
6.How does Aetrix verify that R5F563TCDDFP#V1 is sourced from the original manufacturer or authorized distributors?
All R5F563TCDDFP#V1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F563TCDDFP#V1 meets industry standards.
7.What is the process for return or replacement of R5F563TCDDFP#V1?
All R5F563TCDDFP#V1 units undergo pre-shipment inspection (PSI). If there is an issue with R5F563TCDDFP#V1, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F563TCDDFP#V1 part is unused and in its original packaging.
Return procedure for R5F563TCDDFP#V1:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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