Renesas R5F563TCEDFP#H1
- Part No.:
- R5F563TCEDFP#H1
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 100-LQFP
- Datasheet:
-
R5F563TCEDFP#H1.pdf
- Description:
- 32BIT MCU RX63T LQFP100
- Quantity:
- Payment:

- Shipping:

Inventory:4,027
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Product details
Overview
R5F563TCEDFP#H1 from Renesas is a 100-MHz 32-bit RX CPU-based microcontroller optimized for digital power supply control and motor drive applications. It integrates dual 12-bit ADCs (with three sample-and-hold circuits, programmable gain amplifiers, and window comparators), one 10-bit 20-channel ADC, two 10-bit DACs, USB 2.0 full-speed interface, CAN 2.0B (ISO 11898-1 compliant), and hardware-accelerated Digital Power Supply Controller (DPC) logic. It operates across –40°C to +85°C and targets IEC60730-compliant industrial inverters and SMPS designs.
For engineers reviewing the R5F563TCEDFP#H1 datasheet, R5F563TCEDFP#H1 pinout, R5F563TCEDFP#H1 application, or R5F563TCEDFP#H1 equivalent, this page delivers verified specifications, package mapping to PLQP0100KB-A (100-pin LQFP, 14 × 14 mm, 0.5 mm pitch), confirmed peripheral channel counts, DPC functional scope, and validated alternative MCUs for digital power and motor control use cases.
Technical Context
The R5F563TCEDFP#H1 implements the RXv1 CPU core with IEEE-754 single-precision FPU, 165 DMIPS at 100 MHz, and memory protection unit (MPU). Its clock system supports external crystal (4–12.5 MHz) + PLL, internal 125-kHz LOCO for IWDT, and independent domain clocks (ICLK up to 100 MHz, PCLKA up to 100 MHz, PCLKB up to 50 MHz, PCLKC/PCLKD for ADCs).
It features MTU3 (8-channel 16-bit timer with three-phase complementary PWM), GPT (8-channel 16-bit general PWM timer with dead-time generation and 312-ps PWM delay resolution), and integrated DPC calculation unit using 10-bit ADC measurement results for real-time digital SMPS control - all operating within a single-chip mode configuration.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv1 32-bit CISC Harvard architecture, 100 MHz max, 165 DMIPS, IEEE-754 FPU, MPU support |
| Memory | 384 KB on-chip flash (100 MHz, zero-wait), 32 KB SRAM (100 MHz, zero-wait), 32 KB data flash (100k write/erase cycles) |
| ADC | Two 12-bit S12ADB units (4 channels × 2, simultaneous 7-channel sampling), one 10-bit ADA (20 channels, 0.5 µs/ch @ 100 MHz ADCLK) |
| PWM & Timers | MTU3: 8×16-bit channels with 3-phase complementary output; GPT: 8×16-bit channels with 312-ps PWM delay resolution and interlocking comparator |
| Communication | USB 2.0 full-speed (12 Mbps), CAN 2.0B (1 channel, 32 mailboxes), 5× SCI, 2× RIIC, 2× RSPI, no external bus interface |
| Digital Power Control | Dedicated DPC unit with robust algorithm for switched-mode power supply control, fed by 10-bit ADC measurements |
| Package & Temp | PLQP0100KB-A (100-pin LQFP, 14 × 14 mm, 0.5 mm pitch), –40°C to +85°C (D version) |
Pinout & Package
Package: PLQP0100KB-A - 100-pin LQFP, 14 × 14 mm body, 0.5 mm pitch, exposed thermal pad, RoHS-compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC, VSS | Power supply and ground | Core/IO supply (2.7–3.6 V); separate AVCC/AVSS for analog domains; dedicated VREF pins for ADC/DAC reference |
| XTAL, EXTAL | Main crystal oscillator input/output | Supports 4–12.5 MHz external crystal; enables PLL-based 100 MHz system clock generation |
| MTIOC0A–MTIOC7B | MTU3 waveform I/O | Eight 16-bit timer channels with complementary PWM outputs; used for 3-phase inverter gate driving without CPU overhead |
| GPTIO0A–GPTIO3B | GPT waveform I/O | Four 16-bit general PWM channels with programmable dead time and sub-nanosecond delay resolution for precision timing |
| AD00–AD19 | Analog input channels | 20 dedicated pins for 10-bit ADC (ADA); 8 pins shared between dual 12-bit S12ADB units (AN000–AN007) |
| DA0, DA1 | DAC analog outputs | Two 10-bit voltage-output DACs (0 V to VREF), usable for feedback loop references or bias generation |
| TXD0–RXD4, SCL0–SDA1, MOSI0–SSL1 | Serial interface signals | SCI (5 channels), RIIC (2), RSPI (2) - fully multiplexed on GPIO; USB D+/D− and CANH/CANL are dedicated pins |
| POE0, POE4, POE8, POE10–POE12 | Port Output Enable inputs | Hardware fault detection inputs for MTU3/GPT output pins; trigger immediate high-impedance state on short-circuit or comparator event |
Key Features
| Feature | Design Value |
|---|---|
| Digital Power Supply Controller (DPC) | Hardware-accelerated 16-bit fixed-point calculation unit for real-time SMPS control loops, directly consuming 10-bit ADC conversion results |
| IEC60730 Compliance Support | Oscillation-stop detection, CRC calculator, self-diagnostic A/D, IWDT with dedicated LOCO, frequency measurement circuit (CAC) |
| Precision PWM Timing | 312-ps resolution for PWM edge delay control on GPT channels 0–3, enabling fine-grained dead-time tuning in high-frequency inverters |
| Simultaneous Multi-Channel Sampling | Three ADC units (two 12-bit + one 10-bit) support synchronized sampling across up to 7 analog inputs for current/voltage phase alignment |
| Robust Fault Handling | POE3 module monitors six PWM output pins; triggers hardware-controlled high-Z state on overcurrent or comparator fault without software intervention |
Applications
| Industrial Inverter Control | Digital Switch-Mode Power Supply |
|---|---|
|
Use Scenario: Closed-loop vector control of 3-phase AC induction or PMSM motors in HVAC compressors and industrial drives. IC Role / Device Role / Timing Role: Main controller executing FOC algorithm, generating gate-drive PWM via MTU3/GPT, sampling phase currents with synchronized 12-bit ADCs. Use Value: Hardware-accelerated DPC and sub-nanosecond PWM delay enable stable 20+ kHz switching with minimal CPU load and precise dead-time management. |
Use Scenario: Digital control of isolated DC-DC converters (e.g., LLC resonant, phase-shifted full-bridge) in telecom and server PSUs. IC Role / Device Role / Timing Role: Real-time SMPS controller performing voltage/current regulation, fault protection, and communication via USB/CAN. Use Value: Integrated DPC unit computes compensator outputs directly from 10-bit ADC samples, eliminating external DSP and reducing BOM cost and latency. |
| Motor Drive Reference Design | IEC60730-Certified Appliance Control |
|
Use Scenario: Reference platform for BLDC motor control in white goods (washing machines, refrigerators) with hall-sensor or sensorless commutation. IC Role / Device Role / Timing Role: Central MCU managing commutation sequencing, current sensing, thermal monitoring, and user interface via SCI/USB. Use Value: Dual 12-bit ADCs with programmable gain amplifiers allow direct shunt-based current measurement; POE3 ensures safe shutdown during overcurrent events. |
Use Scenario: Safety-critical control in microwave ovens, induction cooktops, and medical power modules requiring Class B compliance per IEC60730. IC Role / Device Role / Timing Role: Primary safety monitor executing runtime diagnostics: oscillator stop detection, CRC validation, ADC self-test, and IWDT supervision. Use Value: On-chip CAC, IWDT with dedicated LOCO, and ADC self-diagnostic function eliminate need for external safety components and simplify certification. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar digital power and motor control applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F563TEADFP#V1 | 512 KB flash, 48 KB RAM, same package and peripherals; includes CAN module (R5F563TCEDFP#H1 excludes CAN) | Required where CAN bus communication is needed for system-level coordination (e.g., multi-inverter stacks or PLC integration) | Select when CAN 2.0B interface is mandatory; otherwise R5F563TCEDFP#H1 offers identical DPC, PWM, and ADC capability at lower cost. |
| R5F563TBADFP#V1 | 256 KB flash, 24 KB RAM, same package; retains DPC, MTU3, GPT, dual 12-bit ADCs, and IEC60730 features | Suitable for cost-sensitive, lower-complexity SMPS or fan motor control where firmware footprint < 256 KB | Choose for simplified designs with smaller code size; verify flash/RAM margin against toolchain-generated binaries before migration. |
Compared with R5F563TEADFP#V1 and R5F563TBADFP#V1, the R5F563TCEDFP#H1 provides optimal balance of 384 KB flash, 32 KB RAM, full DPC functionality, and IEC60730 support - making it the preferred choice for mid-tier digital power supplies and motor drives where CAN is not required.
Availability
R5F563TCEDFP#H1 is available at Aetrix Electronics and suitable for industrial inverters, digital SMPS, motor drive reference designs, and IEC60730-certified appliance control requiring stable component supply and long-term lifecycle assurance.
Supply support for R5F563TCEDFP#H1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, and power solutions for automotive, industrial, and IoT markets.
The RX63T Group - including R5F563TCEDFP#H1 - was designed specifically for digital power supply control and motor drive applications, integrating hardware accelerators (DPC), high-resolution PWM, and IEC60730 safety features into a single 100-MHz MCU.
FAQ
What is the maximum operating frequency and CPU performance of the R5F563TCEDFP#H1?
The R5F563TCEDFP#H1 operates at a maximum frequency of 100 MHz using the RXv1 32-bit CPU core and delivers 165 DMIPS performance. It includes a single-precision IEEE-754 floating-point unit, 32-bit multiplier (1-cycle execution), and divider (2-cycle execution), enabling efficient real-time control algorithms in digital power and motor applications.
Does the R5F563TCEDFP#H1 include CAN interface functionality?
No, the R5F563TCEDFP#H1 does not include the CAN module. Its part number suffix "C" indicates inclusion of the Digital Power Supply Controller (DPC), while "E" denotes CAN-enabled variants (e.g., R5F563TEADFP#V1). This device retains USB 2.0, SCI, RIIC, and RSPI interfaces but omits CAN hardware.
What ADC resources are available on the R5F563TCEDFP#H1?
The R5F563TCEDFP#H1 integrates two 12-bit S12ADB units (4 channels × 2, with sample-and-hold, programmable gain amplifiers, and window comparators) and one 10-bit ADA unit (20 channels). It supports simultaneous sampling across up to 7 channels using three ADC units - critical for synchronized current/voltage acquisition in motor control.
What is the role of the Digital Power Supply Controller (DPC) in the R5F563TCEDFP#H1?
The DPC in the R5F563TCEDFP#H1 is a dedicated hardware calculation unit for digital switched-mode power supply control. It performs robust fixed-point compensator calculations using real-time 10-bit ADC measurement data - offloading the CPU and enabling deterministic, low-latency regulation loops without external DSP.
Which package and thermal characteristics apply to the R5F563TCEDFP#H1?
The R5F563TCEDFP#H1 uses the PLQP0100KB-A package: a 100-pin LQFP with 14 × 14 mm body, 0.5 mm pitch, and exposed thermal pad. It is rated for operation from –40°C to +85°C (D version), with AVCC/AVCC0 supporting 3.0–3.6 V or 4.0–5.5 V depending on analog rail configuration.
R5F563TCEDFP#H1 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 100-LQFP
- Series:
- RX63T
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RX
- Core Size:
- 32-Bit
- Speed:
- 100MHz
- Connectivity:
- EBI/EMI, I2C, LINbus, SCI, SPI, UART/USART
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 57
- Program Memory Size:
- 384KB (384K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 32K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 12x10b, 8x12b; D/A 2x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F563TCEDFP#H1 FAQ
1.How can I place an order for R5F563TCEDFP#H1 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F563TCEDFP#H1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F563TCEDFP#H1 reliable?
The price and inventory of R5F563TCEDFP#H1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F563TCEDFP#H1 is usually 5 days.
3.What payment methods are accepted for R5F563TCEDFP#H1?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F563TCEDFP#H1 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F563TCEDFP#H1?
R5F563TCEDFP#H1 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F563TCEDFP#H1 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F563TCEDFP#H1?
For technical support, including R5F563TCEDFP#H1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F563TCEDFP#H1 requirements.
6.How does Aetrix verify that R5F563TCEDFP#H1 is sourced from the original manufacturer or authorized distributors?
All R5F563TCEDFP#H1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F563TCEDFP#H1 meets industry standards.
7.What is the process for return or replacement of R5F563TCEDFP#H1?
All R5F563TCEDFP#H1 units undergo pre-shipment inspection (PSI). If there is an issue with R5F563TCEDFP#H1, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F563TCEDFP#H1 part is unused and in its original packaging.
Return procedure for R5F563TCEDFP#H1:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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