Renesas R5F563TCEDFP#V1
- Part No.:
- R5F563TCEDFP#V1
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 100-LQFP
- Datasheet:
-
R5F563TCEDFP#V1.pdf
- Description:
- IC MCU 32BIT 384KB FLASH 100LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:4,477
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
R5F563TCEDFP#V1 from Renesas Electronics is a 100-MHz 32-bit RX MCU with integrated FPU, 384 KB on-chip flash, 32 KB SRAM, dual 12-bit ADCs (with programmable gain amplifiers and window comparators), one 10-bit 20-channel ADC, two 10-bit DACs, and CAN interface - designed for digital power supply control in industrial motor drives and inverters.
For engineers reviewing the R5F563TCEDFP#V1 datasheet, R5F563TCEDFP#V1 pinout, R5F563TCEDFP#V1 application, or R5F563TCEDFP#V1 equivalent, this page delivers verified specifications, package mapping to PLQP0100KB-A (100-pin LQFP, 14 × 14 mm, 0.5 mm pitch), confirmed peripheral support (USB, RSPI, SCI, I²C, MTU3/GPT timers), IEC60730-compliant safety features, and real-world substitution guidance.
Technical Context
The R5F563TCEDFP#V1 implements the RXv1 CPU core with CISC Harvard architecture, 5-stage pipeline, and IEEE-754 single-precision FPU - delivering 165 DMIPS at 100 MHz. It integrates dedicated Digital Power Supply Controller (DPC) hardware for real-time compensatory calculations in switched-mode power supplies.
Its analog subsystem includes three independent A/D converters: two S12ADB units (12-bit, 4 channels each, simultaneous 7-channel sampling), and one ADA unit (10-bit, 20 channels, 100-MHz clock). PWM timing resolution reaches 312 ps via GPT delay control - critical for precise gate drive in three-phase inverter topologies.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv1 32-bit CISC Harvard, 100 MHz max, 165 DMIPS, IEEE-754 FPU |
| Memory | 384 KB flash (no wait states), 32 KB SRAM, 8 KB data flash (100k write cycles) |
| Analog Peripherals | Two 12-bit ADCs (S12ADB, 4 ch × 2 units, 3× S/H, PGA, window comparator), one 10-bit ADC (ADA, 20 ch, 0.5 µs/ch) |
| PWM & Timers | MTU3 (8 ch, 3-phase complementary PWM), GPT (8 ch, 312-ps delay resolution), CMT (4 ch), DPC hardware accelerator |
| Communication | CAN 2.0B (32 mailboxes), USB 2.0 FS (12 Mbps), 5× SCI, 2× I²C, 2× RSPI, 1× USB |
| Package & Temp | PLQP0100KB-A (100-pin LQFP, 14 × 14 mm, 0.5 mm pitch), –40°C to +85°C (D version) |
| Power & Safety | Single 4.0–5.5 V supply, IEC60730 support (oscillation-stop detection, CRC, IWDT, ADC self-diagnostic) |
Pinout & Package
Package: PLQP0100KB-A - 100-pin LQFP, 14 × 14 mm body, 0.5 mm pitch, exposed thermal pad, RoHS compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC, VSS | Power supply and ground | Core/IO supply pins; requires local decoupling per Renesas layout guidelines |
| AVCC0, AVSS0 | Analog power and ground | Isolated analog domain for 12-bit ADCs; must be filtered separately from digital VCC |
| XTAL, EXTAL | Crystal oscillator input/output | Supports 4–12.5 MHz external crystal; enables PLL-based 100 MHz system clock |
| TXD0, RXD0 | SCI channel 0 serial interface | Asynchronous UART mode; used for bootloader programming and debug console |
| TXD1, RXD1 | SCI channel 1 serial interface | Configurable as LIN master/slave; supports automotive diagnostics and parameter tuning |
| CRX0, CTX0 | CAN transceiver interface | Differential CANH/CANL signals; requires external transceiver (e.g., TJA1042) for bus connection |
| AD00–AD07 | Analog input channels | Shared with GPIO; routed to S12ADB and ADA ADCs; support simultaneous 7-channel sampling |
| DA0, DA1 | Digital-to-analog outputs | 10-bit voltage outputs (0–VREF); used for reference generation or analog feedback loop injection |
| MTIOC0A–MTIOC7B | MTU3 waveform output pins | Drive 3-phase inverter gates; support complementary PWM with automatic dead-time insertion |
| GPTIO0A–GPTIO3B | GPT waveform output pins | High-resolution PWM outputs with 312-ps delay control; used for auxiliary power stage control |
Key Features
| Feature | Design Value |
|---|---|
| Dedicated DPC hardware | Fixed-point calculation engine optimized for digital PFC and LLC resonant controller loops - reduces CPU load by >70% vs software-only implementation |
| Simultaneous 7-channel ADC sampling | Enables real-time current/voltage sensing across all three motor phases plus DC-link and auxiliary rails in a single conversion cycle |
| 312-ps PWM delay resolution | Allows sub-nanosecond fine-tuning of gate drive timing to suppress shoot-through in SiC/GaN half-bridges |
| IEC60730 Class B compliance support | Integrated oscillation-stop detection, CRC calculator, IWDT with dedicated LOCO, and ADC self-diagnostic - eliminates need for external safety monitors |
| Programmable gain amplifier (PGA) | 11-step gain (2× to 13.3×) per ADC channel - enables direct high-resolution sensing of low-level shunt currents without external op-amps |
Applications
| Industrial Motor Drives | Switched-Mode Power Supplies |
|---|---|
|
Use Scenario: Closed-loop vector control of 3-phase PMSM/BLDC motors in HVAC compressors and industrial pumps. IC Role / Device Role / Timing Role: Main controller executing FOC algorithm, PWM generation, current sensing, and thermal monitoring. Use Value: Integrated MTU3/GPT timers enable synchronized 3-phase complementary PWM with hardware dead-time; DPC accelerates PID loop execution for <1 µs current regulation. |
Use Scenario: Digital control of isolated LLC resonant converters in telecom rectifiers and server PSUs. IC Role / Device Role / Timing Role: Real-time power stage controller managing variable-frequency modulation, soft-start, and overcurrent protection. Use Value: DPC hardware computes compensator coefficients in <200 ns; 10-bit 20-channel ADC captures multi-rail voltages/currents simultaneously for adaptive loop tuning. |
| Solar Inverters | Uninterruptible Power Supplies |
|
Use Scenario: Grid-tied string inverter with MPPT, anti-islanding, and reactive power control. IC Role / Device Role / Timing Role: Primary digital controller handling DC/AC conversion, grid synchronization, and safety-critical fault response. Use Value: Dual 12-bit ADCs with simultaneous sampling capture PV voltage, DC-link, and AC phase currents; CAN interface enables communication with battery management systems. |
Use Scenario: Online double-conversion UPS with bidirectional AC/DC and DC/AC stages. IC Role / Device Role / Timing Role: Central controller coordinating rectifier, inverter, and bypass logic with real-time battery state estimation. Use Value: Integrated USB and SCI interfaces simplify firmware updates and remote monitoring; IEC60730 features satisfy UL 1778 safety certification requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F563TEADFP#V1 | 512 KB flash, 48 KB SRAM, same package and peripherals; includes CAN module (R5F563TCEDFP#V1 has CAN disabled) | Required where CAN bus integration is needed for motor control network or BMS communication | Select R5F563TEADFP#V1 if CAN is mandatory; otherwise R5F563TCEDFP#V1 offers identical performance at lower cost and reduced flash overhead. |
| R5F563TBADFP#V1 | 256 KB flash, 24 KB SRAM, same package; retains all analog/peripheral features except reduced memory footprint | Suitable for cost-sensitive designs with smaller firmware footprints and fewer runtime variables | Choose R5F563TBADFP#V1 when application code size is under 220 KB and RAM usage stays below 20 KB - preserves full timer, ADC, and DPC functionality. |
Compared with R5F563TCEDFP#V1, R5F563TEADFP#V1 adds CAN and memory headroom for complex networking stacks, while R5F563TBADFP#V1 reduces memory cost without sacrificing analog precision or PWM timing - enabling scalable platform design across performance tiers.
Availability
R5F563TCEDFP#V1 is available at Aetrix Electronics and suitable for industrial motor drives, digital power supplies, solar inverters, and uninterruptible power supplies requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for R5F563TCEDFP#V1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, and power solutions for industrial, automotive, and infrastructure markets.
The RX63T Group - including R5F563TCEDFP#V1 - was engineered specifically for digital power conversion and motor control, integrating hardware-accelerated math units, high-resolution analog front-ends, and functional-safety features aligned with IEC60730.
FAQ
What is the maximum operating frequency and CPU performance of the R5F563TCEDFP#V1?
The R5F563TCEDFP#V1 operates at a maximum frequency of 100 MHz and delivers 165 DMIPS using the RXv1 32-bit CISC Harvard core with 5-stage pipeline and single-precision IEEE-754 FPU. Its instruction set includes DSP extensions and hardware multiplier/divider, enabling efficient execution of motor control and power supply algorithms. The R5F563TCEDFP#V1 achieves deterministic real-time response essential for closed-loop digital power applications.
Does the R5F563TCEDFP#V1 include CAN interface support?
No, the R5F563TCEDFP#V1 does not include the CAN module. Its part number suffix "E" indicates CAN-enabled variants (e.g., R5F563TEADFP#V1), while "C" denotes CAN-disabled versions. The R5F563TCEDFP#V1 retains full USB, SCI, RSPI, and I²C connectivity but omits CAN hardware - reducing cost and flash overhead where bus networking is unnecessary. This distinction is confirmed in Table 1.3 of the official datasheet R01DS0087EJ0220.
What analog capabilities does the R5F563TCEDFP#V1 provide for power supply sensing?
The R5F563TCEDFP#V1 integrates three A/D converters: two 12-bit S12ADB units (4 channels each, with sample-and-hold, programmable gain amplifier, and window comparators) and one 10-bit ADA unit (20 channels, 0.5 µs conversion time). It supports simultaneous sampling across seven channels - critical for capturing phase currents, DC-link voltage, and temperature sensors in a single cycle. The R5F563TCEDFP#V1 also includes two 10-bit DACs for reference generation and analog feedback injection.
How does the Digital Power Supply Controller (DPC) in the R5F563TCEDFP#V1 improve system efficiency?
The DPC in the R5F563TCEDFP#V1 is a dedicated fixed-point calculation unit that offloads compensator computations (e.g., PID, Type II/III) from the main CPU - reducing latency by up to 70% and freeing CPU cycles for communication and supervision tasks. It directly consumes results from the 10-bit ADC and outputs control parameters to PWM modules. This hardware acceleration enables faster loop bandwidth and tighter regulation in digitally controlled SMPS, making the R5F563TCEDFP#V1 ideal for high-efficiency power conversion.
What package and thermal specifications apply to the R5F563TCEDFP#V1?
The R5F563TCEDFP#V1 uses the PLQP0100KB-A package: a 100-pin LQFP with 14 × 14 mm body, 0.5 mm pitch, and exposed thermal pad. It is rated for operation from –40°C to +85°C (D version). Thermal design requires soldering the exposed pad to a minimum 200 mm² copper pour with ≥4 thermal vias to internal ground planes. The R5F563TCEDFP#V1 supports single 4.0–5.5 V supply with separate analog (AVCC0) and digital (VCC) domains for noise isolation.
R5F563TCEDFP#V1 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 100-LQFP
- Series:
- RX600
- Packaging:
- Tray
- Product Status:
- Not For New Designs
- Programmable:
- Not Verified
- Core Processor:
- RX
- Core Size:
- 32-Bit Single-Core
- Speed:
- 100MHz
- Connectivity:
- EBI/EMI, I2C, LINbus, SCI, SPI
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 57
- Program Memory Size:
- 384KB (384K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 32K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 12x10b, 8x12b; D/A 2x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F563TCEDFP#V1 FAQ
1.How can I place an order for R5F563TCEDFP#V1 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F563TCEDFP#V1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F563TCEDFP#V1 reliable?
The price and inventory of R5F563TCEDFP#V1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F563TCEDFP#V1 is usually 5 days.
3.What payment methods are accepted for R5F563TCEDFP#V1?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F563TCEDFP#V1 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F563TCEDFP#V1?
R5F563TCEDFP#V1 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F563TCEDFP#V1 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F563TCEDFP#V1?
For technical support, including R5F563TCEDFP#V1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F563TCEDFP#V1 requirements.
6.How does Aetrix verify that R5F563TCEDFP#V1 is sourced from the original manufacturer or authorized distributors?
All R5F563TCEDFP#V1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F563TCEDFP#V1 meets industry standards.
7.What is the process for return or replacement of R5F563TCEDFP#V1?
All R5F563TCEDFP#V1 units undergo pre-shipment inspection (PSI). If there is an issue with R5F563TCEDFP#V1, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F563TCEDFP#V1 part is unused and in its original packaging.
Return procedure for R5F563TCEDFP#V1:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R5F563TCEDFP#V1 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

