Renesas R5F563TEADFH#V1
- Part No.:
- R5F563TEADFH#V1
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 112-LQFP
- Datasheet:
-
R5F563TEADFH#V1.pdf
- Description:
- IC MCU 32BIT 512KB FLASH 112LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:2,978
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
R5F563TEADFH#V1 from Renesas Electronics is a 112-pin LQFP 32-bit RX MCU optimized for digital power supply control and motor drive applications. It operates at up to 100 MHz, integrates dual 12-bit ADCs (8-channel total with simultaneous 3-channel sampling), one 10-bit ADC (20-channel), two 10-bit DACs, CAN 2.0B interface, USB 2.0 full-speed, and a dedicated Digital Power Supply Controller (DPC) unit - enabling real-time compensatory calculations for switched-mode power supplies.
For engineers reviewing the R5F563TEADFH#V1 datasheet, R5F563TEADFH#V1 pinout, R5F563TEADFH#V1 application, or R5F563TEADFH#V1 equivalent, key selection criteria include its 112-pin PLQP0112JA-A package, -40°C to +85°C operating range, 512 KB on-chip flash with no wait states, 48 KB SRAM, and support for IEC60730-compliant safety functions including oscillation-stop detection, CRC, and self-diagnostic A/D.
Technical Context
The R5F563TEADFH#V1 implements the 32-bit RX CPU core with IEEE-754 single-precision FPU, 165 DMIPS performance at 100 MHz, and CISC Harvard architecture with 5-stage pipeline. Its clock system includes PLL, 125-kHz LOCO for IWDT, and independent clock domains (ICLK up to 100 MHz, PCLKA up to 100 MHz, PCLKB/PCLKC/PCLKD up to 50 MHz).
It features dual timer subsystems: MTU3 (8-channel 16-bit) supporting three-phase complementary PWM with automatic dead-time insertion, and GPT (8-channel 16-bit) with programmable PWM delay resolution down to 312 ps at 100 MHz. The DPC unit performs fixed-point control parameter calculation using 10-bit ADC measurement results.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RX 32-bit, 100 MHz max, 165 DMIPS, IEEE-754 FPU, memory protection unit (MPU) |
| Memory | 512 KB flash (no wait states @100 MHz), 48 KB SRAM, 32 KB data flash (100k erase/write cycles) |
| Analog Peripherals | Two 12-bit ADCs (8 ch, 1 µs/ch @50 MHz ADCLK), one 10-bit ADC (20 ch, 0.5 µs/ch @100 MHz), two 10-bit DACs |
| PWM & Timers | MTU3: 2 × three-phase complementary PWM + 4 × single-phase complementary; GPT: 8-channel with 312-ps PWM delay resolution |
| Communication | CAN 2.0B (32 mailboxes), USB 2.0 full-speed (12 Mbps), 5 × SCI, 2 × RIIC, 2 × RSPI, 1 × LIN-capable SCId |
| Digital Power Control | Dedicated DPC unit with robust control algorithm; uses 10-bit ADC inputs for real-time compensatory calculation in SMPS |
| Safety & Compliance | IEC60730 support: oscillation-stop detection, frequency measurement, CRC, IWDT, A/D self-diagnostic |
Pinout & Package
Package: PLQP0112JA-A, 112-pin LQFP, 20 mm × 20 mm, 0.65 mm pitch, exposed pad, RoHS compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC, VSS | Power supply and ground | Core logic supply (3.0–3.6 V or 4.0–5.5 V); separate analog AVCC/AVCC0 pins for ADC/DAC reference stability |
| XTAL, EXTAL | External crystal oscillator input/output | Supports 4–12.5 MHz crystals for main clock generation; enables high-accuracy timing for PWM and communication |
| TXD0, RXD0 | SCI channel 0 serial interface | Asynchronous UART mode; used for bootloader programming via SCI or debug console communication |
| CAN_TX, CAN_RX | CAN 2.0B physical layer interface | Differential signaling pair compliant with ISO11898-1; supports 1 Mbit/s operation with integrated transceiver drivers |
| USB_VBUS, USB_D+, USB_D− | USB 2.0 full-speed interface | Self-powered or bus-powered operation; integrated transceiver and 2 KB on-chip RAM buffer for endpoint management |
| AD00–AD07 | Analog input channels | Eight dedicated pins for 12-bit S12ADB ADC units; support simultaneous sampling across three channels per unit |
| DA0, DA1 | Digital-to-analog outputs | 10-bit voltage outputs (0 V to VREF); used for feedback loop references or analog control signals in power stages |
| MTIOC0A–MTIOC7B | MTU3 waveform output/input pins | Configurable as complementary PWM outputs for 3-phase inverter gate drives; support hardware dead-time insertion |
Key Features
| Feature | Design Value |
|---|---|
| Digital Power Supply Controller (DPC) | Fixed-point calculation engine dedicated to SMPS compensator design; accepts 10-bit ADC measurements directly for closed-loop parameter updates |
| Simultaneous 3-Channel ADC Sampling | Enables synchronized voltage/current sensing in 3-phase motor or power converter topologies without software overhead |
| Hardware PWM Dead-Time Insertion | Automatic non-overlapping waveform generation in MTU3/GPT eliminates risk of shoot-through in half/full-bridge drivers |
| IEC60730 Safety Functions | On-chip oscillation-stop detection, CRC calculator, IWDT with dedicated LOCO, and A/D self-diagnostic reduce external component count for Class B certification |
| Programmable Gain Amplifier (PGA) | 11-step gain (2× to 13.3×) per ADC channel; allows direct connection of low-level current-sense signals without external op-amps |
| Flexible Clock Domain Partitioning | Independent ICLK (100 MHz), PCLKA (100 MHz), PCLKB/C/D (50 MHz) enable precise timing isolation between CPU, PWM, and ADC subsystems |
Applications
| Industrial Motor Drive | Switch-Mode Power Supply (SMPS) |
|---|---|
|
Use Scenario: Field-oriented control (FOC) of 3-phase BLDC/PMSM motors in HVAC blowers and industrial pumps. IC Role / Device Role / Timing Role: Real-time execution of FOC algorithms, generation of six complementary PWM signals with sub-ns timing precision, and synchronized current/voltage sampling. Use Value: Eliminates need for external FPGA or DSP; MTU3's hardware dead-time and simultaneous ADC sampling ensure safe, efficient inverter switching. |
Use Scenario: Digital control of isolated DC-DC converters (e.g., LLC resonant, phase-shifted full-bridge) in telecom and server PSUs. IC Role / Device Role / Timing Role: Closed-loop regulation using DPC unit, real-time ADC acquisition of primary-side current and secondary-side voltage, and precise PWM timing for zero-voltage switching. Use Value: DPC offloads compensator math from CPU; 312-ps PWM delay resolution enables fine-tuning of resonant timing margins. |
| Automotive Body Control Module (BCM) | Uninterruptible Power Supply (UPS) |
|
Use Scenario: Centralized control of lighting, window lift, and seat actuation with CAN network integration. IC Role / Device Role / Timing Role: CAN 2.0B node managing distributed peripherals; SCI/USB for diagnostics and firmware updates; ADC for battery voltage monitoring. Use Value: Single-chip solution reduces BOM cost and board space; IEC60730 compliance simplifies functional safety documentation for ASIL-B systems. |
Use Scenario: Online double-conversion UPS with line-interactive topology and battery charge/discharge management. IC Role / Device Role / Timing Role: Simultaneous monitoring of AC input, DC bus, battery voltage, and load current; coordinated control of inverter, rectifier, and charger stages. Use Value: Dual ADC units allow concurrent sampling of 7 analog channels; 10-bit DACs generate precise reference voltages for analog control loops. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F563TCADFH#V1 | 384 KB flash, 32 KB RAM, same 112-pin package and peripheral set; lacks 128 KB flash and 16 KB RAM of R5F563TEADFH#V1 | Suitable for cost-sensitive designs with reduced firmware footprint and lower RAM usage requirements | Select when application code size stays under 384 KB and real-time buffers fit within 32 KB SRAM |
| R5F563TEADFB#V1 | 144-pin LQFP (PLQP0144KA-A), adds external bus interface and 23 additional GPIO; identical core, memory, and analog specs | Required for systems needing parallel memory expansion or >110 GPIO (e.g., multi-sensor industrial HMI) | Choose only if external bus access or extra I/O is mandatory; otherwise R5F563TEADFH#V1 offers better PCB area efficiency |
Compared with R5F563TCADFH#V1, the R5F563TEADFH#V1 provides 128 KB more flash and 16 KB more RAM for complex control algorithms and data logging; versus R5F563TEADFB#V1, it trades 32 fewer GPIO and no external bus for compact 112-pin layout - ideal for space-constrained power electronics modules.
Availability
R5F563TEADFH#V1 is available at Aetrix Electronics and suitable for industrial motor drives, digital power supplies, automotive body controllers, and uninterruptible power supply systems requiring stable component supply, long-term lifecycle support, and IEC60730-compliant safety features.
Supply support for R5F563TEADFH#V1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, and power solutions for industrial, automotive, and infrastructure markets.
The RX63T Group, including R5F563TEADFH#V1, was designed specifically for high-precision digital power conversion and motor control - integrating dedicated hardware accelerators (DPC, MTU3, GPT) and safety features to replace discrete analog controllers and external DSPs.
FAQ
What is the maximum operating frequency and CPU performance of the R5F563TEADFH#V1?
The R5F563TEADFH#V1 operates at a maximum frequency of 100 MHz and delivers 165 DMIPS of processing performance. Its 32-bit RX CPU core includes a single-precision IEEE-754 floating-point unit, two multiply-and-accumulate units, and a 5-stage pipeline - enabling deterministic execution of complex motor control and power supply algorithms without external co-processors.
Does the R5F563TEADFH#V1 support IEC60730 functional safety compliance?
Yes, the R5F563TEADFH#V1 includes multiple hardware features required for Class B IEC60730 compliance: oscillation-stop detection, clock frequency accuracy measurement circuit (CAC), independent watchdog timer (IWDT) with dedicated 125-kHz LOCO, CRC calculator, and self-diagnostic function for the A/D converter. These reduce software validation burden and eliminate need for external safety monitors.
What analog peripherals are integrated into the R5F563TEADFH#V1?
The R5F563TEADFH#V1 integrates two 12-bit ADC units (8 channels total, with simultaneous 3-channel sampling per unit), one 10-bit ADC (20 channels), two 10-bit DACs, and a programmable gain amplifier (11 gain steps). It also includes window comparators and sample-and-hold circuits - enabling complete analog signal chain handling for current/voltage sensing and feedback control in power electronics.
How does the Digital Power Supply Controller (DPC) in the R5F563TEADFH#V1 function?
The DPC in the R5F563TEADFH#V1 is a dedicated fixed-point calculation unit that executes compensator algorithms for switched-mode power supplies. It accepts raw 10-bit ADC measurements directly, performs robust control calculations (e.g., PID, lead-lag), and outputs updated duty-cycle parameters - all without CPU intervention, ensuring deterministic timing and freeing the RX core for higher-layer tasks.
What package and pin count does the R5F563TEADFH#V1 use?
The R5F563TEADFH#V1 uses the PLQP0112JA-A package: a 112-pin LQFP measuring 20 mm × 20 mm with 0.65 mm pitch and an exposed thermal pad. This package supports all core peripherals including CAN, USB, dual ADCs, and MTU3/GPT timers - while offering smaller footprint than 144-pin alternatives for space-constrained power module designs.
R5F563TEADFH#V1 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 112-LQFP
- Series:
- RX600
- Packaging:
- Tray
- Product Status:
- Not For New Designs
- Programmable:
- Not Verified
- Core Processor:
- RX
- Core Size:
- 32-Bit Single-Core
- Speed:
- 100MHz
- Connectivity:
- CANbus, EBI/EMI, I2C, LINbus, SCI, SPI, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 69
- Program Memory Size:
- 512KB (512K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 48K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 5.5V
- Data Converters:
- A/D 12x10b, 8x12b; D/A 2x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F563TEADFH#V1 FAQ
1.How can I place an order for R5F563TEADFH#V1 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F563TEADFH#V1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F563TEADFH#V1 reliable?
The price and inventory of R5F563TEADFH#V1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F563TEADFH#V1 is usually 5 days.
3.What payment methods are accepted for R5F563TEADFH#V1?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F563TEADFH#V1 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F563TEADFH#V1?
R5F563TEADFH#V1 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F563TEADFH#V1 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F563TEADFH#V1?
For technical support, including R5F563TEADFH#V1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F563TEADFH#V1 requirements.
6.How does Aetrix verify that R5F563TEADFH#V1 is sourced from the original manufacturer or authorized distributors?
All R5F563TEADFH#V1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F563TEADFH#V1 meets industry standards.
7.What is the process for return or replacement of R5F563TEADFH#V1?
All R5F563TEADFH#V1 units undergo pre-shipment inspection (PSI). If there is an issue with R5F563TEADFH#V1, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F563TEADFH#V1 part is unused and in its original packaging.
Return procedure for R5F563TEADFH#V1:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R5F563TEADFH#V1 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

