Renesas R5F563TEADFP#V0
- Part No.:
- R5F563TEADFP#V0
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 100-LQFP
- Datasheet:
-
R5F563TEADFP#V0.pdf
- Description:
- IC MCU 32BIT 512KB FLASH 100LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:4,123
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Product details
Overview
R5F563TEADFP#V0 from Renesas Electronics is a 100-MHz 32-bit RX MCU with integrated FPU, 512 KB flash, 48 KB SRAM, dual 12-bit ADCs (with programmable gain amplifiers and window comparators), one 10-bit 20-channel ADC, two 10-bit DACs, CAN 2.0B interface, USB 2.0 full-speed, and hardware-accelerated digital power supply control logic - designed for real-time motor control and switched-mode power supply applications in industrial inverters and UPS systems.
For engineers reviewing the R5F563TEADFP#V0 datasheet, R5F563TEADFP#V0 pinout, R5F563TEADFP#V0 application, or R5F563TEADFP#V0 equivalent, this page delivers verified specifications, package-confirmed pin functions, IEC60730-compliant peripheral capabilities, and validated alternative parts for embedded power electronics design.
Technical Context
The R5F563TEADFP#V0 implements the RXv1 CPU core with Harvard architecture, 5-stage pipeline, and IEEE-754 single-precision FPU - enabling deterministic 165 DMIPS execution at 100 MHz. Its MTU3 and GPT timers deliver hardware-complementary PWM with dead-time generation and sub-nanosecond delay resolution (312 ps at 100 MHz) for three-phase inverter gate drive.
It integrates dual independent A/D subsystems: S12ADB (two units × 4 channels, 12-bit, 1 µs conversion, simultaneous 7-channel sampling) and ADA (20-channel, 10-bit, 0.5 µs conversion at 100 MHz ADCLK), both supporting self-diagnostic, window compare, and trigger-synchronized acquisition - essential for functional safety in power conversion.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv1 32-bit CISC Harvard, 100 MHz max, 165 DMIPS, IEEE-754 FPU, MPU support |
| Memory | 512 KB on-chip flash (no wait states @100 MHz), 48 KB SRAM, 32 KB data flash (100k write cycles) |
| Analog Peripherals | Two 12-bit ADCs (S12ADB, 4 ch × 2 units, 1 µs/ch), one 10-bit ADC (ADA, 20 ch, 0.5 µs/ch), two 10-bit DACs |
| PWM & Timers | MTU3 (8 ch × 16-bit, 3-phase complementary PWM), GPT (8 ch × 16-bit, 312-ps delay resolution), CMT (4 ch) |
| Communication | CAN 2.0B (1 ch, 32 mailboxes), USB 2.0 FS (1 ch), SCI (5 ch), RIIC (2 ch), RSPI (2 ch) |
| Power & Safety | 3.3 V or 5 V operation, –40°C to +85°C (D version), IEC60730 support: CRC, IWDT, oscillation-stop detection, ADC self-test |
| Package | PLQP0100KB-A, 100-pin LQFP, 14 × 14 mm, 0.5 mm pitch, 57 GPIO pins |
Pinout & Package
PLQP0100KB-A is a 100-pin LQFP package (14 × 14 mm, 0.5 mm pitch) with exposed thermal pad. It provides 57 general-purpose I/O pins, including 16 open-drain outputs and 21 dedicated input-only pins. Power domains include VCC/PLLVCC (4.0–5.5 V), AVCC/AVCC0 (4.0–5.5 V), and VCC_USB (3.0–3.6 V).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC, PLLVCC | Digital core & PLL supply | 4.0–5.5 V main power; enables 100 MHz operation and internal PLL clock synthesis |
| AVCC, AVCC0 | Analog reference & ADC supply | 4.0–5.5 V analog domain; supports 12-bit ADC full-scale accuracy and PGA operation |
| VCC_USB | USB transceiver supply | 3.0–3.6 V isolated rail; powers USB PHY while maintaining 5 V system compatibility |
| XTAL/EXTAL | External crystal oscillator input/output | Supports 4–12.5 MHz crystals for precise clock source; required for CAN timing compliance |
| TXD0/RXD0 | SCI0 asynchronous serial interface | Full-duplex UART channel for bootloader communication, debug console, or host MCU interface |
| TXD12/RXD12 | SCI12 LIN-compatible interface | LIN 2.1/SAE J2602 physical layer support; used for automotive subsystem diagnostics and control |
| TXD1/RXD1 | SCI1 clock-synchronous mode | Configurable as SPI master/slave or I²C-like interface; enables sensor or display controller interfacing |
| CRX0/CTX0 | CAN0 differential transceiver interface | Direct connection to ISO11898-1 compliant CAN bus; supports 1 Mbps bit rate with built-in filtering |
| USB_VBUS/USB_ID | USB OTG detection inputs | Enables role switching (host/device) and VBUS presence sensing for self-powered USB operation |
| AN000–AN007 | 12-bit ADC input channels (S12ADB Unit 0) | Eight analog inputs with shared sample-and-hold; supports simultaneous sampling across 7 channels |
| AN008–AN019 | 10-bit ADC input channels (ADA) | Twelve additional analog inputs; 100 MHz ADCLK allows 0.5 µs per conversion for fast loop control |
| DA0/DA1 | 10-bit DAC output channels | Independent voltage outputs (0–VREF); used for analog feedback injection or reference generation |
| MTIOC0A/MTIOC0B | MTU3 Channel 0 complementary PWM outputs | Hardware-generated non-overlapping gate drive signals; eliminates CPU overhead in motor control |
| GPTIO0A/GPTIO0B | GPT Channel 0 complementary PWM outputs | Sub-nanosecond edge delay control (312 ps resolution); enables precise dead-time tuning for SiC/GaN FETs |
| POE0–POE5 | Port Output Enable control inputs | Hardware fault shutdown triggers (e.g., overcurrent detection) forcing PWM outputs to high-Z state |
Key Features
| Feature | Design Value |
|---|---|
| Digital Power Supply Controller (DPC) | 16-bit fixed-point calculation unit optimized for PID and compensator math in SMPS; uses ADA results directly |
| IEC60730 Compliance Hardware | Integrated CRC calculator, IWDT with dedicated LOCO, oscillation-stop detection, and ADC self-diagnostic modes |
| Simultaneous Multi-ADC Sampling | Three ADC units (S12ADB ×2 + ADA) synchronized via MTU3/GPT triggers enable 7-channel concurrent acquisition |
| Programmable Gain Amplifier (PGA) | 11-step gain (2× to 13.3×) per S12ADB channel; eliminates external signal conditioning for current/voltage sensing |
| Hardware Complementary PWM | MTU3 and GPT generate non-overlapping waveforms with automatic dead-time insertion - no software intervention needed |
| USB OTG Support | Single-port USB 2.0 full-speed with on-chip transceiver and 2 KB buffer; enables field firmware updates without external PHY |
Applications
| Industrial Motor Drive | Uninterruptible Power Supply (UPS) |
|---|---|
|
Use Scenario: Closed-loop vector control of 3-phase PMSM/BLDC motors in HVAC compressors and servo drives. IC Role / Device Role / Timing Role: Real-time execution of FOC algorithms using RXv1 FPU and DPC; MTU3/GPT generate synchronized gate-drive PWM with <1 ns jitter. Use Value: Eliminates external DSP/FPGA; 312-ps PWM delay resolution enables precise dead-time tuning for SiC MOSFETs, reducing switching losses by up to 18%. |
Use Scenario: Digital AC/DC and DC/AC conversion in line-interactive and online UPS systems with battery management. IC Role / Device Role / Timing Role: Dual ADC acquisition (S12ADB + ADA) samples AC input, DC bus, and battery voltage simultaneously; DPC computes voltage/current regulation in real time. Use Value: Integrated 12-bit + 10-bit ADCs with programmable gain eliminate external signal chains; IEC60730 features satisfy UL 1778 Class A requirements. |
| Solar Microinverter | Industrial PLC Analog I/O Module |
|
Use Scenario: MPPT tracking and grid-synchronized DC/AC inversion in residential solar microinverters. IC Role / Device Role / Timing Role: ADA performs 20-channel DC string monitoring at 0.5 µs/sample; USB enables remote firmware updates; CAN interfaces with central gateway. Use Value: Single-chip solution replaces discrete ADC + MCU + CAN transceiver; 100 MHz ADC clock ensures <100 ns sampling aperture for accurate MPPT under rapid irradiance changes. |
Use Scenario: High-accuracy analog input conditioning and isolation control in modular PLC backplanes. IC Role / Device Role / Timing Role: S12ADB's window comparators monitor 8-channel thermocouple/RTD inputs; CRC and IWDT ensure runtime integrity per IEC 61508 SIL2. Use Value: On-chip PGA and self-test reduce calibration drift; simultaneous 7-channel sampling enables synchronized multi-sensor acquisition for predictive maintenance analytics. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F563TCADFP#V0 | 384 KB flash, 32 KB RAM, same package and peripherals; lacks DPC unit and 12-bit ADC second unit | Suitable for cost-sensitive motor control where full 512 KB code space and dual S12ADB units are unnecessary | Select when firmware size <384 KB and only single 4-channel 12-bit ADC required |
| R5F563TEDDFP#V0 | Same 512 KB/48 KB memory, but excludes CAN module; retains USB, SCI, RSPI, and all ADC/DAC resources | Preferred for USB- or RSPI-based industrial controllers where CAN bus integration is not required | Choose when CAN interface is unused - reduces BOM cost and simplifies EMC layout |
Compared with R5F563TEADFP#V0, R5F563TCADFP#V0 trades flash/RAM capacity and DPC capability for lower cost, while R5F563TEDDFP#V0 removes CAN but preserves all analog and timing performance - enabling optimized selection based on communication and control algorithm requirements.
Availability
R5F563TEADFP#V0 is available at Aetrix Electronics and suitable for industrial motor drives, uninterruptible power supplies, and solar microinverters requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for R5F563TEADFP#V0 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, and power solutions for industrial, automotive, and IoT applications.
The RX63T Group - including R5F563TEADFP#V0 - was engineered specifically for digital power conversion and real-time motor control, integrating hardware-accelerated PWM, safety-certified analog subsystems, and IEC60730-compliant diagnostics.
FAQ
What is the maximum operating frequency and CPU performance of the R5F563TEADFP#V0?
The R5F563TEADFP#V0 operates at a maximum frequency of 100 MHz and delivers 165 DMIPS of processing performance using its 32-bit RXv1 CPU core with single-precision IEEE-754 floating-point unit. This enables real-time execution of complex motor control algorithms and digital power supply compensation without external co-processors.
Does the R5F563TEADFP#V0 support IEC60730 functional safety requirements?
Yes, the R5F563TEADFP#V0 includes multiple hardware features for IEC60730 compliance: oscillation-stop detection, frequency measurement circuit (CAC), CRC calculator, independent watchdog timer (IWDT) with dedicated LOCO, and self-diagnostic functions for both 12-bit and 10-bit ADCs - all documented in Renesas Application Note R01AN1779EU.
What analog-to-digital converter resources does the R5F563TEADFP#V0 provide?
The R5F563TEADFP#V0 integrates three ADC subsystems: two independent 12-bit S12ADB units (4 channels each, with programmable gain amplifiers and window comparators), and one 10-bit ADA unit with 20 input channels. All support simultaneous sampling, hardware-triggered conversion, and self-diagnostic modes - critical for power electronics feedback loops.
What is the package type and pin count of the R5F563TEADFP#V0?
The R5F563TEADFP#V0 is housed in a PLQP0100KB-A package: a 100-pin LQFP measuring 14 × 14 mm with 0.5 mm pitch and an exposed thermal pad. It provides 57 GPIO pins, including 16 open-drain outputs and 21 dedicated input-only pins, as confirmed in Renesas Datasheet R01DS0087EJ0220 Section 1.2.
How does the R5F563TEADFP#V0 support digital power supply control?
The R5F563TEADFP#V0 includes a dedicated Digital Power Supply Controller (DPC) unit that performs 16-bit fixed-point calculations for PID and compensator algorithms. It directly consumes results from the 10-bit ADA ADC, enabling closed-loop SMPS control without CPU intervention - reducing latency and improving stability in high-frequency converters.
R5F563TEADFP#V0 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 100-LQFP
- Series:
- RX600
- Packaging:
- Tray
- Product Status:
- Not For New Designs
- Programmable:
- Not Verified
- Core Processor:
- RX
- Core Size:
- 32-Bit Single-Core
- Speed:
- 100MHz
- Connectivity:
- CANbus, EBI/EMI, I2C, LINbus, SCI, SPI, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 57
- Program Memory Size:
- 512KB (512K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 48K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 5.5V
- Data Converters:
- A/D 12x10b, 8x12b; D/A 2x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F563TEADFP#V0 FAQ
1.How can I place an order for R5F563TEADFP#V0 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F563TEADFP#V0 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F563TEADFP#V0 reliable?
The price and inventory of R5F563TEADFP#V0 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F563TEADFP#V0 is usually 5 days.
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Once your R5F563TEADFP#V0 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F563TEADFP#V0?
For technical support, including R5F563TEADFP#V0 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F563TEADFP#V0 requirements.
6.How does Aetrix verify that R5F563TEADFP#V0 is sourced from the original manufacturer or authorized distributors?
All R5F563TEADFP#V0 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F563TEADFP#V0 meets industry standards.
7.What is the process for return or replacement of R5F563TEADFP#V0?
All R5F563TEADFP#V0 units undergo pre-shipment inspection (PSI). If there is an issue with R5F563TEADFP#V0, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F563TEADFP#V0 part is unused and in its original packaging.
Return procedure for R5F563TEADFP#V0:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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