Renesas R5F563TEBDFP#V0
- Part No.:
- R5F563TEBDFP#V0
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 100-LQFP
- Datasheet:
-
R5F563TEBDFP#V0.pdf
- Description:
- IC MCU 32BIT 512KB FLASH 100LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:4,904
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
R5F563TEBDFP#V0 from Renesas is a 100-MHz 32-bit RX CPU-based microcontroller with integrated FPU, 512 KB flash, 48 KB SRAM, dual 12-bit ADCs (with programmable gain amplifiers and window comparators), one 10-bit 20-channel ADC, two 10-bit DACs, CAN 2.0B interface, USB 2.0 full-speed, and MTU3/GPT PWM timers optimized for digital power supply control in industrial inverters and motor drives.
For engineers reviewing the R5F563TEBDFP#V0 datasheet, R5F563TEBDFP#V0 pinout, R5F563TEBDFP#V0 application, or R5F563TEBDFP#V0 equivalent, this MCU delivers deterministic real-time control with IEC60730-compliant self-diagnostic features, 312-ps PWM delay resolution, and hardware-accelerated digital power supply calculation - critical for high-reliability AC/DC and DC/DC converter designs.
Technical Context
The R5F563TEBDFP#V0 implements the RXv1 CPU core with Harvard architecture, 5-stage pipeline, and IEEE-754 single-precision FPU - enabling 165 DMIPS at 100 MHz. Its clock system integrates PLL, LOCO oscillators, and CAC for frequency accuracy measurement across main, PLL, and IWDT clocks.
It features dual A/D subsystems: S12ADB (two units × 4 channels, 1.0 µs conversion at 50 MHz PCLKD) with simultaneous 7-channel sampling, and ADA (20-channel, 0.5 µs at 100 MHz ADCLK); plus DPC hardware for fixed-point compensator calculations using 10-bit ADC inputs - all supporting IEC60730 Class B compliance.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv1 32-bit CISC Harvard, 100 MHz max, 165 DMIPS, IEEE-754 FPU |
| Memory | 512 KB on-chip flash (no wait states), 48 KB SRAM, 32 KB data flash (100k erase cycles) |
| Analog Peripherals | Two 12-bit ADCs (S12ADB, 4 ch × 2 units), one 10-bit ADC (ADA, 20 ch), two 10-bit DACs |
| PWM & Timers | MTU3 (8 ch, 3-phase complementary PWM), GPT (8 ch, 312-ps delay resolution), CMT (4 ch) |
| Communication | CAN 2.0B (1 ch, 32 mailboxes), USB 2.0 FS (1 ch), SCI (5 ch), RIIC (2 ch), RSPI (2 ch) |
| Digital Power Features | Digital Power Controller (DPC) unit, oscillation-stop detection, CRC, IWDT, ADC self-diagnosis |
| Operating Range | –40°C to +85°C (D version), 2.7–3.6 V VCC, 3.0–3.6 V or 4.0–5.5 V AVCC |
Pinout & Package
Package: PLQP0100KB-A, 100-pin LQFP (14 × 14 mm, 0.5 mm pitch), RoHS-compliant, moisture sensitivity level 3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC, VSS | Power supply and ground | Core logic supply (2.7–3.6 V) and reference return; decoupling required per datasheet layout guidelines |
| AVCC0, AVSS0 | Analog power and ground | Separate 3.0–3.6 V or 4.0–5.5 V analog domain for ADC/DAC; isolated from digital VCC to minimize noise coupling |
| XTAL, EXTAL | External crystal oscillator input/output | Supports 4–12.5 MHz crystals for precise clock generation; optional external clock input mode |
| MTIOC0A–MTIOC7B | MTU3 waveform I/O | Dedicated pins for complementary PWM output, input capture, and phase counting - enable 3-phase inverter gate drive without CPU overhead |
| ADTRG0–ADTRG3 | A/D conversion trigger inputs | Hardware-synchronized start signals for S12ADB and ADA converters - ensure deterministic timing with PWM or timer events |
| CAN_TX, CAN_RX | CAN bus physical layer interface | Differential signaling pair compliant with ISO11898-1; requires external transceiver and termination resistors |
| USB_DP, USB_DM | USB 2.0 full-speed differential pair | Integrated transceiver supports 12 Mbps; requires 1.5 kΩ pull-up on DP for device enumeration |
Key Features
| Feature | Design Value |
|---|---|
| IEC60730 Compliance Engine | Hardware CRC, IWDT with dedicated LOCO, oscillation-stop detection, ADC self-diagnostic, and frequency measurement - reduces software certification burden |
| Digital Power Controller (DPC) | Fixed-point calculation unit accelerates PID/compensator math using 10-bit ADC results - enables real-time digital control loop execution |
| High-Resolution PWM Timing | GPT supports 312-ps PWM edge delay (at 100 MHz ICLK) - allows precise dead-time tuning and adaptive timing compensation in SMPS |
| Simultaneous Multi-ADC Sampling | S12ADB supports 7-channel simultaneous sampling across three units - captures synchronized voltage/current waveforms for vector control |
| Robust Debug & Security | FINE two-wire and JTAG interfaces; register write protection; MPU for memory isolation - supports secure development and field firmware updates |
Applications
| Industrial Inverter Control | Digital AC/DC Converter |
|---|---|
Use Scenario: Closed-loop control of 3-phase induction motors in HVAC and pump drives requiring torque precision and thermal safety. IC Role / Device Role / Timing Role: Primary real-time controller executing FOC algorithms, generating complementary PWM via MTU3, and monitoring current/voltage via synchronized ADC sampling. Use Value: Hardware-accelerated DPC and 312-ps PWM delay enable adaptive dead-time compensation - reducing switching losses and improving efficiency over temperature. |
Use Scenario: Digital control of resonant LLC and active clamp forward topologies in telecom and server PSUs. IC Role / Device Role / Timing Role: System-on-chip controller managing PWM generation, voltage/current regulation, fault response, and USB-based configuration via built-in USB FS interface. Use Value: Integrated 10-bit 20-channel ADC and dual 12-bit ADCs allow simultaneous sensing of primary-side and secondary-side parameters - eliminating external multiplexers and reducing BOM cost. |
| Motor Drive Reference Design | IEC60730-Certified Appliance MCU |
Use Scenario: Reference platform for BLDC and PMSM drives targeting UL/EN 60730 Class B compliance. IC Role / Device Role / Timing Role: Central timing and safety monitor - coordinating MTU3 PWM, GPT-triggered ADC conversions, and IWDT reset supervision. Use Value: On-chip oscillation-stop detection and hardware CRC reduce need for external watchdog ICs - simplifying design and improving time-to-certification. |
Use Scenario: Smart home appliance control (e.g., washing machine drum motor, compressor) requiring functional safety diagnostics. IC Role / Device Role / Timing Role: Safety-critical MCU performing periodic ADC self-test, memory integrity checks, and clock accuracy validation during runtime. Use Value: Dedicated IWDT with independent 125-kHz LOCO ensures fail-safe reset even if main PLL fails - meeting mandatory fault reaction time requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F563TEADFP#V0 | Same package and memory, but 4.0–5.5 V VCC/PLLVCC supply; includes CAN module | Targeted at 5-V industrial systems with CAN bus integration; not suitable for 3.3-V-only designs | Select when operating from 5-V rail and CAN communication is mandatory |
| R5F563TCBDFP#V0 | 384 KB flash, 32 KB RAM, same 2.7–3.6 V supply and package; includes CAN | Lower memory footprint for cost-sensitive digital power applications where full 512 KB is unnecessary | Choose for reduced BOM cost in volume production where code size fits within 384 KB |
Compared with R5F563TEBDFP#V0, R5F563TEADFP#V0 supports higher supply voltage but lacks 3.3-V optimization, while R5F563TCBDFP#V0 trades flash/RAM capacity for lower unit cost - both retain identical peripheral sets and DPC functionality for digital power control.
Availability
R5F563TEBDFP#V0 is available at Aetrix Electronics and suitable for industrial motor drives, digital power supplies, and IEC60730-certified appliances requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for R5F563TEBDFP#V0 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, and power solutions for industrial, automotive, and IoT markets.
The RX63T Group - including R5F563TEBDFP#V0 - was designed specifically for digital power supply control and motor inverter applications, integrating hardware accelerators (DPC), high-resolution PWM, and IEC60730 safety features into a single chip.
FAQ
What is the maximum operating frequency and CPU performance of the R5F563TEBDFP#V0?
The R5F563TEBDFP#V0 operates at a maximum frequency of 100 MHz and delivers 165 DMIPS using the RXv1 32-bit CPU core with integrated IEEE-754 single-precision FPU. Its 5-stage pipeline, variable-length instructions, and on-chip multiplier/divider enable deterministic real-time execution - essential for digital power control loops and motor FOC algorithms running on the R5F563TEBDFP#V0.
Does the R5F563TEBDFP#V0 include a CAN interface, and what version is supported?
Yes, the R5F563TEBDFP#V0 includes one CAN 2.0B-compliant channel with 32 configurable mailboxes, supporting both standard and extended frames per ISO11898-1. This interface is fully integrated and does not require external transceivers - though an external CAN transceiver must still be used for physical layer connection. The CAN module is enabled in this part variant as confirmed in Table 1.3 of the R01DS0087EJ0220 datasheet for R5F563TEBDFP#V0.
What analog peripherals are integrated into the R5F563TEBDFP#V0?
The R5F563TEBDFP#V0 integrates two 12-bit ADC units (S12ADB, 4 channels each), one 10-bit 20-channel ADC (ADA), and two 10-bit DAC channels. The S12ADB units support simultaneous 7-channel sampling, programmable gain amplifiers (11 gain steps), and window comparators. All ADCs include self-diagnostic functions for IEC60730 compliance - key capabilities documented for the R5F563TEBDFP#V0 in the RX63T Group datasheet.
How does the Digital Power Controller (DPC) function in the R5F563TEBDFP#V0?
The DPC in the R5F563TEBDFP#V0 is a dedicated fixed-point calculation unit that accelerates compensator math (e.g., PID, Type II/III) for switched-mode power supplies. It directly consumes results from the 10-bit ADA converter and outputs control values to PWM timers - offloading the CPU and enabling sub-microsecond loop times. This hardware accelerator is explicitly enabled in R5F563TEBDFP#V0 per datasheet Table 1.2 and is central to its digital power supply use case.
What package and pin count does the R5F563TEBDFP#V0 use?
The R5F563TEBDFP#V0 uses the PLQP0100KB-A package: a 100-pin LQFP measuring 14 × 14 mm with 0.5 mm pitch. It provides 57 GPIO pins, including 16 open-drain outputs and 21 input-only pins, and supports external bus expansion with four CS areas. This package is confirmed in Table 1.3 of the R01DS0087EJ0220 datasheet for the R5F563TEBDFP#V0 orderable part number.
R5F563TEBDFP#V0 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 100-LQFP
- Series:
- RX600
- Packaging:
- Tray
- Product Status:
- Not For New Designs
- Programmable:
- Not Verified
- Core Processor:
- RX
- Core Size:
- 32-Bit Single-Core
- Speed:
- 100MHz
- Connectivity:
- CANbus, EBI/EMI, I2C, LINbus, SCI, SPI, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 57
- Program Memory Size:
- 512KB (512K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 48K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 12x10b, 8x12b; D/A 2x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F563TEBDFP#V0 FAQ
1.How can I place an order for R5F563TEBDFP#V0 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F563TEBDFP#V0 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F563TEBDFP#V0 reliable?
The price and inventory of R5F563TEBDFP#V0 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F563TEBDFP#V0 is usually 5 days.
3.What payment methods are accepted for R5F563TEBDFP#V0?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F563TEBDFP#V0 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F563TEBDFP#V0?
R5F563TEBDFP#V0 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F563TEBDFP#V0 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F563TEBDFP#V0?
For technical support, including R5F563TEBDFP#V0 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F563TEBDFP#V0 requirements.
6.How does Aetrix verify that R5F563TEBDFP#V0 is sourced from the original manufacturer or authorized distributors?
All R5F563TEBDFP#V0 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F563TEBDFP#V0 meets industry standards.
7.What is the process for return or replacement of R5F563TEBDFP#V0?
All R5F563TEBDFP#V0 units undergo pre-shipment inspection (PSI). If there is an issue with R5F563TEBDFP#V0, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F563TEBDFP#V0 part is unused and in its original packaging.
Return procedure for R5F563TEBDFP#V0:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R5F563TEBDFP#V0 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

