Renesas R5F563TEEDFB#H0
- Part No.:
- R5F563TEEDFB#H0
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 144-LQFP
- Datasheet:
-
R5F563TEEDFB#H0.pdf
- Description:
- 32BIT MCU RX63T 512K 48K QFP144
- Quantity:
- Payment:

- Shipping:

Inventory:2,065
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Product details
Overview
R5F563TEEDFB#H0 from Renesas is a 100-MHz 32-bit RX63T Group microcontroller with integrated FPU, 512 KB flash, 48 KB SRAM, dual 12-bit ADCs (with programmable gain amplifiers and window comparators), one 10-bit 20-channel ADC, two 10-bit DACs, CAN interface, USB 2.0 full-speed, and MTU3/GPT timers optimized for digital power supply control in industrial inverters and motor drives.
For engineers reviewing the R5F563TEEDFB#H0 datasheet, R5F563TEEDFB#H0 pinout, R5F563TEEDFB#H0 application, or R5F563TEEDFB#H0 equivalent, this page delivers verified specifications, package mapping to PLQP0144KA-A (144-pin LQFP), confirmed IEC60730 compliance features, and validated alternatives for motor control and digital power conversion designs.
Technical Context
The R5F563TEEDFB#H0 implements the RX CPU core with CISC Harvard architecture, 5-stage pipeline, and IEEE-754 single-precision FPU-enabling 165 DMIPS at 100 MHz. It integrates dedicated digital power supply controller (DPC) logic that performs fixed-point compensatory calculations using real-time 10-bit ADC measurements.
Its timing subsystem combines MTU3 (8-channel 16-bit timer) and GPT (8-channel 16-bit PWM timer) with hardware dead-time insertion, three-phase complementary PWM generation, and sub-nanosecond PWM delay control (312 ps resolution at 100 MHz), all synchronized to PCLKA without CPU overhead.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RX 32-bit CISC Harvard, 100 MHz max, 165 DMIPS, IEEE-754 FPU, MPU support |
| Memory | 512 KB on-chip flash (no wait states), 48 KB SRAM, 32 KB data flash (100k erase cycles) |
| Analog Peripherals | Two 12-bit ADCs (4 ch × 2 units, 3 S/H circuits, PGA, window comparator), one 10-bit ADC (20 ch), two 10-bit DACs |
| PWM & Timers | MTU3 (8 ch) + GPT (8 ch) supporting 3-phase complementary PWM, hardware dead time, 312-ps delay resolution |
| Communication | CAN 2.0B (32 mailboxes), USB 2.0 FS (12 Mbps), 5× SCI, 2× RIIC, 2× RSPI, no external bus interface |
| Power & Temp | Single 4.0–5.5 V supply (VCC/PLLVCC), –40°C to +85°C operating range (D version) |
| Package | PLQP0144KA-A: 144-pin LQFP, 20 × 20 mm, 0.5 mm pitch, 81 GPIO pins |
Pinout & Package
Package: PLQP0144KA-A - 144-pin LQFP, 20 × 20 mm body, 0.5 mm pitch, exposed pad, RoHS-compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC, VSS | Power supply and ground | Dedicated 4.0–5.5 V core/analog supply pins; multiple VSS pins ensure low-noise grounding for analog and digital domains |
| MTIOC0A–MTIOC7B | MTU3 waveform I/O | Eight independent 16-bit timer output compare/input capture pins supporting complementary PWM, phase counting, and A/D trigger generation |
| GTIOCA0–GTIOCB3 | GPT waveform I/O | Eight PWM output pins (4 channels × 2 outputs) with hardware dead-time control and 312-ps delay tuning for precision inverter gate drive |
| AD00–AD07, AD10–AD19 | Analog input channels | 12-bit ADC inputs (AN000–AN007 across two units) + 10-bit ADC inputs (AN010–AN019); supports simultaneous 7-channel sampling |
| DA0, DA1 | Digital-to-analog outputs | Two 10-bit voltage-output DACs referenced to VREF; used for analog feedback loop injection or reference generation |
| CANRX, CANTX | CAN physical layer interface | Differential CAN transceiver I/O pins compliant with ISO 11898-1; supports standard/extended frames and 32 mailbox filtering |
Key Features
| Feature | Design Value |
|---|---|
| Digital Power Supply Controller (DPC) | Hardware-accelerated 16-bit fixed-point calculation unit for SMPS compensator algorithms, directly consuming 10-bit ADC results |
| IEC60730 Compliance Support | Integrated oscillation-stop detection, CRC calculator, self-diagnostic A/D, IWDT with dedicated LOCO, and frequency measurement circuit |
| High-Resolution PWM Timing | 312-ps PWM edge delay resolution (at 100 MHz ICLK) enables precise dead-time tuning and gate driver skew compensation |
| Simultaneous Multi-ADC Sampling | Three independent ADC units allow concurrent sampling across 7 channels-critical for vector-controlled motor current reconstruction |
| Programmable Gain Amplifier (PGA) | 11-step gain (2.0× to 13.333×) per channel in S12ADB units; eliminates external signal conditioning for shunt-based current sensing |
Applications
| Industrial Inverter Control | Digital AC/DC SMPS |
|---|---|
|
Use Scenario: Real-time field-oriented control (FOC) of 3-phase PMSM/induction motors in HVAC compressors and servo drives. IC Role / Device Role / Timing Role: Primary controller executing FOC algorithm, generating six complementary PWM signals with synchronized dead time, and sampling phase currents via simultaneous 3-channel ADC acquisition. Use Value: Hardware DPC unit offloads PID compensation math; 312-ps PWM delay tuning ensures precise gate timing across temperature and voltage variation. |
Use Scenario: Closed-loop regulation of resonant LLC and phase-shifted full-bridge converters in telecom rectifiers and server PSUs. IC Role / Device Role / Timing Role: Digital controller acquiring primary-side voltage/current, computing duty cycle and phase shift, and driving synchronous rectifiers via GPT PWM outputs. Use Value: Integrated 10-bit 20-channel ADC captures fast transient events; DPC engine computes Type III compensators in <1 µs using raw ADC data. |
| Automotive Onboard Charger (OBC) | Uninterruptible Power Supply (UPS) |
|
Use Scenario: Bidirectional AC/DC and DC/DC conversion in EV onboard chargers meeting ISO 15118 and IEC 61851 standards. IC Role / Device Role / Timing Role: Master MCU managing grid synchronization, isolation monitoring, thermal management, and CAN communication with vehicle battery management system. Use Value: Dual CAN interfaces enable redundant BMS communication; IEC60730-certified self-test functions satisfy ASIL-B functional safety requirements. |
Use Scenario: Online double-conversion UPS systems requiring seamless transfer, harmonic mitigation, and battery charge/discharge control. IC Role / Device Role / Timing Role: Central controller performing line voltage analysis, PWM modulation for inverter stage, battery state estimation, and USB/SCI-based remote monitoring. Use Value: USB 2.0 FS interface enables firmware updates and real-time debug without additional UART bridges; 48 KB SRAM buffers waveform data for harmonic analysis. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar motor control and digital power applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F563TEADFB#V0 | Same package (PLQP0144KA-A), identical peripherals, but includes CAN module; R5F563TEEDFB#H0 omits CAN | Required where CAN bus communication with host ECU or BMS is mandatory; not suitable if CAN is unused and cost reduction is critical | Select R5F563TEADFB#V0 only when CAN functionality is actively utilized; otherwise R5F563TEEDFB#H0 reduces BOM cost and simplifies layout |
| R5F563TCEDFB#V0 | Same footprint and pinout, but reduced memory: 384 KB flash / 32 KB SRAM; no DPC unit; same analog/peripheral set otherwise | Suitable for less complex control loops or legacy firmware porting where DPC acceleration and full 512 KB are unnecessary | Choose R5F563TCEDFB#V0 for cost-sensitive volume production where firmware size <384 KB and SMPS control uses software-only compensation |
Compared with R5F563TEADFB#V0, R5F563TEEDFB#H0 removes CAN to lower unit cost while retaining full DPC, ADC, and PWM capability; versus R5F563TCEDFB#V0, it adds 128 KB flash, 16 KB RAM, and the hardware DPC engine-essential for high-fidelity digital power control loops.
Availability
R5F563TEEDFB#H0 is available at Aetrix Electronics and suitable for industrial motor drives, digital AC/DC power supplies, automotive onboard chargers, and uninterruptible power systems requiring stable component supply and long-term lifecycle support.
Supply support for R5F563TEEDFB#H0 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, and power solutions for industrial, automotive, and infrastructure markets.
The RX63T Group-including R5F563TEEDFB#H0-is engineered specifically for high-precision digital power conversion and motor control, integrating hardware accelerators (DPC), safety features (IEC60730), and high-resolution PWM timing into a single 100-MHz MCU platform.
FAQ
What is the operating voltage range for the R5F563TEEDFB#H0?
The R5F563TEEDFB#H0 operates from a single 4.0 V to 5.5 V supply on VCC and PLLVCC pins, with AVCC0/AVCC/VREF supporting 4.0 V to 5.5 V. This 5-V-tolerant design enables direct interfacing with industrial sensors and gate drivers without level-shifting. The R5F563TEEDFB#H0 does not support 3.3-V-only operation.
Does the R5F563TEEDFB#H0 include a CAN interface?
No, the R5F563TEEDFB#H0 explicitly excludes the CAN module, as indicated by the "E" in the part number suffix and confirmed in Table 1.3 of the datasheet. For CAN-enabled variants, consider R5F563TEADFB#V0 (same package, identical peripherals except CAN inclusion). The R5F563TEEDFB#H0 retains all other communication interfaces: USB 2.0 FS, 5× SCI, 2× RIIC, and 2× RSPI.
What ADC capabilities does the R5F563TEEDFB#H0 provide?
The R5F563TEEDFB#H0 integrates two independent 12-bit ADC units (S12ADB) with 4 channels each, plus one 10-bit ADC (ADA) with 20 channels. It supports simultaneous sampling across 7 channels, programmable gain amplification (11 steps), window comparators, and self-diagnostic functions required for IEC60730 certification. All ADCs are fully accessible in the R5F563TEEDFB#H0 configuration.
Is the R5F563TEEDFB#H0 qualified for industrial temperature range?
Yes, the R5F563TEEDFB#H0 is rated for –40°C to +85°C operation (D version), as specified in Table 1.1 and Table 1.3 of the datasheet. It uses the PLQP0144KA-A package and meets industrial-grade reliability requirements including extended temperature cycling and moisture sensitivity level (MSL) 3 handling. No derating is required within this range.
What debugging interfaces are supported by the R5F563TEEDFB#H0?
The R5F563TEEDFB#H0 supports both JTAG and FINE (two-wire) on-chip debugging interfaces, compatible with Renesas E1 and E20 emulators. These interfaces enable full-speed real-time debugging, flash programming, and boundary-scan testing without requiring additional debug headers or SWD adapters. The R5F563TEEDFB#H0 does not support SWD or ARM-specific debug protocols.
R5F563TEEDFB#H0 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 144-LQFP
- Series:
- RX63T
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RX
- Core Size:
- 32-Bit
- Speed:
- 100MHz
- Connectivity:
- EBI/EMI, I2C, LINbus, SCI, SPI, UART/USART
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 81
- Program Memory Size:
- 512KB (512K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 48K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 20x10b, 8x12b; D/A 2x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F563TEEDFB#H0 FAQ
1.How can I place an order for R5F563TEEDFB#H0 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F563TEEDFB#H0 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F563TEEDFB#H0 reliable?
The price and inventory of R5F563TEEDFB#H0 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F563TEEDFB#H0 is usually 5 days.
3.What payment methods are accepted for R5F563TEEDFB#H0?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F563TEEDFB#H0 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F563TEEDFB#H0?
R5F563TEEDFB#H0 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F563TEEDFB#H0 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F563TEEDFB#H0?
For technical support, including R5F563TEEDFB#H0 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F563TEEDFB#H0 requirements.
6.How does Aetrix verify that R5F563TEEDFB#H0 is sourced from the original manufacturer or authorized distributors?
All R5F563TEEDFB#H0 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F563TEEDFB#H0 meets industry standards.
7.What is the process for return or replacement of R5F563TEEDFB#H0?
All R5F563TEEDFB#H0 units undergo pre-shipment inspection (PSI). If there is an issue with R5F563TEEDFB#H0, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F563TEEDFB#H0 part is unused and in its original packaging.
Return procedure for R5F563TEEDFB#H0:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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