Renesas R5F564MFCDLC#21
- Part No.:
- R5F564MFCDLC#21
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 177-TFLGA
- Datasheet:
-
R5F564MFCDLC#21.pdf
- Description:
- IC MCU 32BIT 2MB FLASH 177TFLGA
- Quantity:
- Payment:

- Shipping:

Inventory:319
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Product details
Overview
R5F564MFCDLC#21 from Renesas is a 120-MHz 32-bit RXv2 microcontroller with integrated FPU, 4 MB code flash, 512 KB SRAM, IEEE 1588-compliant dual Ethernet MAC, full-speed USB 2.0 with battery charging, CAN (3 channels), and 12-bit A/D (29 total channels). It targets industrial automation controllers requiring real-time deterministic communication, secure firmware execution, and high-precision analog sensing.
For engineers reviewing the R5F564MFCDLC#21 datasheet, R5F564MFCDLC#21 pinout, R5F564MFCDLC#21 application, or R5F564MFCDLC#21 equivalent, key selection criteria include its 177-pin TFLGA package, dual Ethernet + PTP support, on-chip AES/SHA encryption, 32 KB ECC RAM for safety-critical data, and IEC60730 compliance features including self-diagnostic A/D and oscillation-stop detection.
Technical Context
The R5F564MFCDLC#21 implements the RXv2 CPU core with 240 DMIPS at 120 MHz, single-precision IEEE-754 FPU, and dual multiply-accumulate units. Its memory subsystem includes 4 MB zero-wait-state code flash, 64 KB reprogrammable data flash (100k cycles), and 512 KB SRAM - 32 KB of which features SEC-DED ECC for ASIL-B–capable systems.
Peripheral architecture integrates dual ETHERC modules with EPTPC (IEEE 1588 v2) and EDMAC (3-channel DMA), USBA with 8.5 KB buffer and battery charging support, three CAN modules (32 mailboxes each), and two independent 12-bit S12ADC units (8 + 21 channels) with self-diagnostic voltage generation and analog disconnection detection.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit, 120 MHz max, 240 DMIPS, IEEE-754 FPU, 2× MAC units |
| Memory | 4 MB code flash (no wait states), 64 KB data flash (100k write cycles), 512 KB SRAM, 32 KB ECC RAM (SEC-DED) |
| Package & Pins | 177-pin TFLGA (8 mm × 8 mm, 0.5 mm pitch), 127 general-purpose I/O pins (19 with 5-V tolerance) |
| Ethernet | Dual IEEE 802.3 10/100 Mbps MAC with IEEE 1588-2008 PTP hardware timestamping and cut-through forwarding |
| USB | Full-speed USB 2.0 host/function with battery charging (USBA), 8.5 KB on-chip buffer, no external resistors required |
| Analog | Two 12-bit ADCs: S12AD0 (8 ch), S12AD1 (21 ch); conversion time 0.48 µs @12-bit; self-diagnostic & disconnection detection |
| Security | AES-128/192/256, DES/TDES, SHA-1/224/256, HMAC; Trusted Memory blocks 8–9 protect firmware against read-out |
Pinout & Package
Package: PTTLG0177KA-A (177-pin TFLGA, 8 mm × 8 mm, 0.5 mm pitch, 0.75 mm height).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC, AVCC0, AVCC1 | Power supply inputs | Core (2.7–3.6 V), analog domain 0 & 1; separate LDO domains enable noise isolation for ADC/DAC |
| VBATT | Battery backup supply | Enables RTC operation during main power loss; supports calendar/clock retention without system reset |
| ETXD0–ETXD3, ETXCK, ETXEN, ERXD0–ERXD3, ERXDV, ERXER | Ethernet PHY interface (Channel 0) | MII-compatible 8-bit parallel interface; supports 10/100 Mbps full/half-duplex with hardware flow control |
| USBDP, USBDM | USB 2.0 differential data pair | Integrated transceiver with battery charging detection logic; supports BC1.2 CDP/DCP modes |
| AD00–AD28 | Analog input channels | 29 dedicated pins mapped to S12AD0 (AD00–AD07) and S12AD1 (AD08–AD28); all support sample-and-hold |
| MTIOC0A–MTIOC8B | MTU3 timer I/O | 28 PWM/complementary PWM output pins with programmable dead-time insertion for motor inverter control |
Key Features
| Feature | Design Value |
|---|---|
| IEC60730 Class B Support | Oscillation-stop detection, CRC calculator, IWDTa windowed watchdog, A/D self-test voltages, register write protection |
| Dual IEEE 1588 Ethernet | Hardware timestamping accuracy ±50 ns; PTP event message handling offloads CPU; cut-through reduces inter-frame latency |
| Secure Boot & Firmware Protection | Trusted Memory blocks 8–9 prevent external read-out; AES decryption engine enables encrypted flash loading |
| Real-Time Determinism | ELC (Event Link Controller) enables direct peripheral-to-peripheral triggering (e.g., TPU → ADC start) without CPU intervention |
| Industrial Analog Integrity | Two independent 12-bit ADCs with per-channel sampling time control, disconnection detection, and dual-trigger redundancy mode |
Applications
| Industrial PLC Controller | Smart Energy Gateway |
|---|---|
|
Use Scenario: Programmable logic controller executing ladder logic and motion control loops with synchronized I/O scanning. IC Role / Device Role / Timing Role: Main application processor managing dual Ethernet for PROFINET RT/IRT, CANopen fieldbus, and real-time ADC sampling at 100 kSPS. Use Value: MTU3 complementary PWM outputs drive 3-phase inverters with hardware-dead-time compensation; ELC links timer events to ADC triggers for jitter-free sampling. |
Use Scenario: Two-way energy meter gateway aggregating data from smart meters via RS485 (SCIg), RF mesh (sub-GHz via SPI), and cellular backhaul. IC Role / Device Role / Timing Role: Secure edge node performing TLS 1.2 encryption (AES/SHA), IEEE 1588 time synchronization across distributed meters, and SDHI logging of outage events. Use Value: On-chip AES-256 accelerates TLS handshake; PTP hardware timestamping aligns meter readings within ±100 ns across LAN; SDHI supports 4-bit bus for 15 MB/s logging. |
| Medical Infusion Pump | Building HVAC BMS Controller |
|
Use Scenario: Safety-certified infusion pump delivering precise fluid dosing with pressure monitoring, motor control, and wireless telemetry. IC Role / Device Role / Timing Role: ASIL-B–capable controller running IEC62304 software, monitoring analog pressure sensors (S12AD1), driving stepper motors (GPTA PWM), and transmitting alerts via USB CDC. Use Value: 32 KB ECC RAM stores critical therapy parameters; A/D self-diagnostic confirms sensor integrity before each dose; IWDTa windowed timeout prevents runaway delivery. |
Use Scenario: Central building management system coordinating HVAC actuators, CO₂ sensors, occupancy detectors, and chiller plant interfaces. IC Role / Device Role / Timing Role: Multi-protocol hub supporting BACnet/IP (Ethernet), Modbus RTU (SCIg), and KNX (SCIh), with local PID loop execution on RXv2 core. Use Value: Dual Ethernet enables redundant BACnet/IP uplinks; SCIh LIN support interfaces with low-cost occupancy sensors; temperature sensor provides on-die ambient reference for calibration. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F565NEHDFP#30 | Same RX65N Group; 144-pin LQFP; 2 MB flash; no USBA (USBb only); single Ethernet; 128 KB SRAM | Lacks battery charging USB, PTP hardware, and second Ethernet channel; lower I/O count (111 pins) | Select when cost-sensitive designs omit dual Ethernet and USB charging, and fit within 144-pin layout constraints. |
| R7FA6M2AF3CFP#AA0 | RX72M Group; 200 MHz; 2 MB flash; single Ethernet; no PTP; 192 KB SRAM; TrustZone-enabled | Higher CPU performance but no IEEE 1588 hardware; TrustZone replaces MPU for security partitioning | Prefer for new designs needing higher compute throughput and Arm TrustZone over PTP precision and dual MAC. |
Compared with R5F564MFCDLC#21, the R5F565NEHDFP#30 sacrifices dual Ethernet, PTP, and USB battery charging for lower cost and smaller footprint, while the R7FA6M2AF3CFP#AA0 trades PTP hardware and dual MAC for Arm-based TrustZone security and higher clock speed - making R5F564MFCDLC#21 uniquely suited for time-synchronized industrial networking where sub-100 ns timestamping and redundant Ethernet are mandatory.
Availability
R5F564MFCDLC#21 is available at Aetrix Electronics and suitable for industrial PLCs, smart energy gateways, medical infusion pumps, and building HVAC BMS controllers requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for R5F564MFCDLC#21 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader headquartered in Tokyo, Japan, specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.
The RX64M Group - including R5F564MFCDLC#21 - was designed specifically for industrial automation and networked equipment requiring deterministic real-time performance, functional safety certification (IEC60730), and integrated secure communication (Ethernet/USB/CAN).
FAQ
What is the maximum operating frequency and CPU architecture of the R5F564MFCDLC#21?
The R5F564MFCDLC#21 operates at a maximum frequency of 120 MHz using the 32-bit RXv2 CPU core, delivering 240 DMIPS performance. It includes a single-precision IEEE-754 floating-point unit, dual multiply-accumulate units, and a 5-stage Harvard pipeline with variable-length instructions for ultra-compact code density. This architecture enables deterministic real-time execution essential for industrial control loops and motion profiling in the R5F564MFCDLC#21.
Does the R5F564MFCDLC#21 support IEEE 1588 Precision Time Protocol, and how is it implemented?
Yes, the R5F564MFCDLC#21 integrates a dedicated PTP controller (EPTPC) compliant with IEEE 1588-2008 (v2), connected directly to both Ethernet MAC channels. Hardware timestamping achieves ±50 ns accuracy on transmit/receive frames, and the EPTPC handles event message processing without CPU involvement. This enables the R5F564MFCDLC#21 to serve as a boundary clock or transparent clock in time-sensitive networking applications such as synchronized PLCs and distributed I/O systems.
What analog peripherals are included in the R5F564MFCDLC#21, and what safety features do they provide?
The R5F564MFCDLC#21 includes two independent 12-bit A/D converters: S12AD0 (8 channels) and S12AD1 (21 channels), with conversion times as fast as 0.48 µs. Both units feature built-in self-diagnostic capability generating internal reference voltages (VREFL0/VREFH0 and AVSS1/AVCC1), analog input disconnection detection, and dual-trigger redundancy mode. These functions are certified for IEC60730 Class B compliance and ensure reliable sensor monitoring in safety-critical applications running on the R5F564MFCDLC#21.
How does the R5F564MFCDLC#21 handle USB connectivity, and what distinguishes its USBA module?
The R5F564MFCDLC#21 features a full-speed USB 2.0 host/function module (USBA) with integrated transceiver and 8.5 KB on-chip RAM buffer - supporting battery charging detection per USB Battery Charging Specification 1.2 (BC1.2). Unlike the standard USBb module, USBA enables CDP/DCP modes and eliminates need for external pull-up/down resistors. This makes the R5F564MFCDLC#21 ideal for embedded devices requiring field-upgradable firmware via USB while powering peripherals - a key capability in industrial HMI and gateway applications.
What package type and pin count does the R5F564MFCDLC#21 use, and what I/O capabilities does it offer?
The R5F564MFCDLC#21 uses a 177-pin TFLGA package (PTLG0177KA-A, 8 mm × 8 mm, 0.5 mm pitch) with 127 general-purpose I/O pins - 19 of which are 5-V tolerant. It supports open-drain outputs, programmable pull-up resistors, and switchable drive strength. The pinout allocates dedicated signals for dual Ethernet MII, USB DP/DM, 29 ADC inputs, and 28 MTU3 PWM outputs - enabling complex industrial interfacing without external level shifters or glue logic in the R5F564MFCDLC#21 design.
R5F564MFCDLC#21 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 177-TFLGA
- Series:
- RX600
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- RXv2
- Core Size:
- 32-Bit Single-Core
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, SCI, SPI, SSI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 127
- Program Memory Size:
- 2MB (2M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 64K x 8
- RAM Size:
- 552K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 29x12b; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F564MFCDLC#21 FAQ
1.How can I place an order for R5F564MFCDLC#21 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F564MFCDLC#21 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F564MFCDLC#21 reliable?
The price and inventory of R5F564MFCDLC#21 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F564MFCDLC#21 is usually 5 days.
3.What payment methods are accepted for R5F564MFCDLC#21?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F564MFCDLC#21 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F564MFCDLC#21?
R5F564MFCDLC#21 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F564MFCDLC#21 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F564MFCDLC#21?
For technical support, including R5F564MFCDLC#21 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F564MFCDLC#21 requirements.
6.How does Aetrix verify that R5F564MFCDLC#21 is sourced from the original manufacturer or authorized distributors?
All R5F564MFCDLC#21 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F564MFCDLC#21 meets industry standards.
7.What is the process for return or replacement of R5F564MFCDLC#21?
All R5F564MFCDLC#21 units undergo pre-shipment inspection (PSI). If there is an issue with R5F564MFCDLC#21, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F564MFCDLC#21 part is unused and in its original packaging.
Return procedure for R5F564MFCDLC#21:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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