Renesas R5F564MFDDFB#31
- Part No.:
- R5F564MFDDFB#31
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 144-LQFP
- Datasheet:
-
R5F564MFDDFB#31.pdf
- Description:
- IC MCU 32BIT 2MB FLASH 144LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:124
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Product details
Overview
R5F564MFDDFB#31 from Renesas is a 32-bit RXv2 microcontroller operating at up to 120 MHz (240 DMIPS), featuring on-chip 4 MB flash, 512 KB SRAM, IEEE 1588-compliant dual Ethernet MAC, full-speed USB 2.0 with battery charging, CAN, SD host interface, and hardware AES/SHA encryption - deployed in industrial gateways requiring real-time protocol bridging and secure edge processing.
For engineers reviewing the R5F564MFDDFB#31 datasheet, R5F564MFDDFB#31 pinout, R5F564MFDDFB#31 application, or R5F564MFDDFB#31 equivalent, key selection criteria include its 176-pin LFBGA package (PLQP0176KB-A), dual Ethernet + USB + CAN coexistence, 12-bit dual A/D with self-diagnostic, and support for IEC60730 Class B functional safety compliance.
Technical Context
The R5F564MFDDFB#31 implements the RXv2 CPU core with single-precision IEEE-754 FPU, two MAC units, and CISC Harvard architecture with 5-stage pipeline - enabling deterministic real-time execution at 120 MHz. It integrates dual independent Ethernet controllers (ETHERC) with PTP timestamping (EPTPC) and dedicated EDMAC channels, supporting MII/RMII and wake-on-LAN.
Its clock system combines external crystal (8–24 MHz), internal HOCO/LOCO oscillators, and PLL for flexible domain partitioning: ICLK up to 120 MHz, PCLKA up to 120 MHz (for ETHERC/USBA/AES), PCLKB up to 60 MHz (for timers/ADC), and separate ADCLK domains for dual S12AD units - ensuring precise timing isolation across mixed-criticality peripherals.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit, 120 MHz max, 240 DMIPS, IEEE-754 FPU, 5-stage pipeline |
| Memory | 4 MB code flash (no wait states @120 MHz), 64 KB data flash (100k erase cycles), 512 KB SRAM, 32 KB ECC RAM, 8 KB standby RAM |
| Connectivity | Dual IEEE 1588 Ethernet MAC (MII/RMII), USB 2.0 FS with battery charging (USBA), 3× CAN (ISO 11898-1), 4× SCIFA, 2× RIIC, QSPI, SDHI |
| Analog | Two 12-bit A/D converters (8 + 21 channels), 2× 12-bit D/A, on-chip temperature sensor (±1°C), self-diagnostic & disconnection detection |
| Security | Optional AES-128/192/256, DES/T-DES, SHA-1/224/256, HMAC, trusted memory (blocks 8–9 protected) |
| Power & Temp | 2.7–3.6 V supply, 0.3 mA/MHz typical active current, –40°C to +85°C (D-version), four low-power modes including deep software standby |
| Safety | IEC60730 Class B support: oscillation-stop detection, CRC, IWDTa, A/D self-test, register write protection |
Pinout & Package
Package: PLQP0176KB-A, 176-pin LFBGA, 24 × 24 mm, 0.5 mm pitch, RoHS compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Core & analog power supply | Separate 2.7–3.6 V domains for digital logic and ADC/DAC reference stability |
| VBATT | Battery backup supply | Enables RTC operation during main power loss; connects to coin-cell or supercap |
| XTAL / EXTAL | Main crystal oscillator input/output | Supports 8–24 MHz external crystal for high-accuracy system clock and Ethernet timing |
| MD0–MD3 | Mode setting pins | Determine boot mode (SCI/USB/user), single-chip vs extended mode, and endian configuration at reset |
| ETXD0–7 / ETXCK / ETRXDV / ERXDV / ERXD0–7 | Ethernet PHY interface | MII interface signals for dual Ethernet channels; RMII supported via pin multiplexing |
| USBDP / USBDM | USB 2.0 differential pair | Full-speed (12 Mbps) USB transceiver I/O; integrated termination and pull-up control |
| TXD0 / RXD0 | SCI0 serial interface | Asynchronous UART for debug console or host communication; supports LIN via SCIh |
| AD00–AD07 / AD10–AD20 | Analog inputs | Two independent A/D units: unit 0 (8 ch), unit 1 (21 ch); each with programmable sampling time & disconnection detection |
Key Features
| Feature | Design Value |
|---|---|
| Dual IEEE 1588 Ethernet MAC | Hardware timestamping, PTP event/message handling, and cut-through frame transfer between channels reduce latency for time-sensitive industrial protocols |
| USB 2.0 FS with battery charging | Integrated USBA module with 8.5 KB buffer supports BC1.2-compliant charging detection and enumeration without external PHY |
| IEC60730 Class B readiness | On-chip oscillation-stop detection, CRC accelerator, IWDTa with window function, and A/D self-test enable certified functional safety implementation |
| Event Link Controller (ELC) | 119 internal event sources routed without CPU intervention - e.g., TPU trigger → A/D start → DMA transfer → interrupt, minimizing jitter and ISR overhead |
| Secure boot & trusted memory | Option-setting memory controls read protection for flash blocks 8–9; enables secure bootloader storage and firmware integrity enforcement |
| Flexible clock domain partitioning | Independent ICLK, PCLKA–D, FCLK, BCLK allow optimization of power/performance trade-offs per peripheral group (e.g., 120 MHz for Ethernet, 60 MHz for ADC) |
Applications
| Industrial Ethernet Gateway | Secure Edge PLC Controller |
|---|---|
|
Use Scenario: Protocol translation between Modbus TCP, EtherNet/IP, and CANopen in factory automation networks. IC Role / Device Role / Timing Role: Dual Ethernet MAC handles concurrent master/slave roles; USBA enables field-service USB configuration; CAN interfaces legacy machinery. Use Value: Hardware PTP timestamping ensures sub-microsecond synchronization across distributed I/O nodes without external timing hardware. |
Use Scenario: Compact, safety-certified PLC running ladder logic with local I/O expansion and remote diagnostics. IC Role / Device Role / Timing Role: RXv2 core executes deterministic control loops; IEC60730 features validate runtime integrity; SDHI stores program logs and firmware updates. Use Value: On-chip ECC RAM and A/D self-test meet SIL2 requirements; 512 KB SRAM accommodates real-time OS and application code in one chip. |
| Smart Energy Meter Hub | Networked Building Controller |
|
Use Scenario: Aggregating AMI data from multiple smart meters via RS485 (SCIg) and forwarding over Ethernet or cellular backhaul. IC Role / Device Role / Timing Role: Dual Ethernet provides redundant LAN uplinks; QSPI boots from encrypted firmware image; AES engine secures meter data payloads. Use Value: Hardware crypto acceleration achieves >10 Mbps AES-GCM throughput, enabling end-to-end encryption without compromising polling cycle time. |
Use Scenario: HVAC/BAS controller managing BACnet MS/TP, LonWorks, and KNX devices while reporting to cloud platforms via Ethernet/Wi-Fi bridge. IC Role / Device Role / Timing Role: Multiple SCIg/SCIFA channels drive legacy field buses; RTC with battery backup maintains schedule integrity during outages. Use Value: 127 GPIOs with 5-V tolerance simplify interfacing to diverse sensors/actuators; 12-bit A/D resolves thermistor and pressure transducer inputs with ±0.1% linearity. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-performance industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F565NEHDFB#30 | Same RX65N Group, 176-pin LFBGA, but adds 1 MB SRAM, 8 MB flash, and enhanced security (TRNG, RSA), no USB battery charging | Targeted at higher-end secure IoT edge nodes requiring larger code footprint and asymmetric crypto | Select when needing TRNG/RSA and >4 MB flash; not drop-in due to different USB feature set and memory map |
| R7FA6M2AF3CFB#AA0 | RX72M-based, 176-pin LFBGA, 240 MHz CPU, single Ethernet, no USB battery charging, added 2D graphics accelerator | Optimized for HMI-integrated controllers where display rendering and motion control coexist | Choose for GUI + motion control synergy; lacks dual Ethernet and USB BC, so unsuitable for gateway use cases |
Compared with R5F564MFDDFB#31, R5F565NEHDFB#30 offers greater memory and crypto depth but sacrifices USB battery charging, while R7FA6M2AF3CFB#AA0 trades dual Ethernet for graphics acceleration - making R5F564MFDDFB#31 uniquely balanced for protocol-rich, security-aware industrial gateways.
Availability
R5F564MFDDFB#31 is available at Aetrix Electronics and suitable for industrial gateways, edge PLCs, smart energy hubs, and networked building controllers requiring stable component supply, long-term lifecycle assurance, and automotive-grade reliability under extended temperature operation.
Supply support for R5F564MFDDFB#31 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for industrial, automotive, and enterprise applications.
The RX64M Group, including R5F564MFDDFB#31, was designed for high-integrity industrial connectivity - integrating dual Ethernet, USB, CAN, and functional safety features into a single 120 MHz MCU for protocol gateway and edge control applications.
FAQ
What is the package type and pin count of the R5F564MFDDFB#31?
The R5F564MFDDFB#31 uses a 176-pin LFBGA package (PLQP0176KB-A) measuring 24 × 24 mm with 0.5 mm pitch. This package supports all dual Ethernet, USB, CAN, and high-pin-count peripheral features documented for the RX64M Group. Pin compatibility is confirmed per Renesas datasheet R01DS0173EJ0120, page 1.
Does the R5F564MFDDFB#31 support IEEE 1588 Precision Time Protocol?
Yes, the R5F564MFDDFB#31 integrates a dedicated PTP controller (EPTPC) linked to both Ethernet MACs, enabling hardware timestamping of PTP event messages (Sync, Delay_Req, etc.) with nanosecond resolution. This capability is explicitly specified in Section 1.1 and Table 1.1 of the R01DS0173EJ0120 datasheet.
What are the key differences between the R5F564MFDDFB#31 and the R5F565NEHDFB#30?
The R5F564MFDDFB#31 and R5F565NEHDFB#30 share the same 176-pin LFBGA package and RXv2 core, but differ in memory (4 MB flash vs 8 MB), security (AES/SHA only vs AES/SHA/RSA/TRNG), and USB (battery charging enabled vs disabled). The R5F565NEHDFB#30 also omits USB battery charging functionality per its datasheet R01DS0227EJ0100.
Can the R5F564MFDDFB#31 operate in extended temperature ranges?
Yes, the R5F564MFDDFB#31 is rated for –40°C to +85°C (D-version), as confirmed in Section 1.1 "Operating temp. range" of the R01DS0173EJ0120 datasheet. It does not support the G-version (–40°C to +105°C); that rating applies only to select RX64M variants such as R5F564MGDDFB#31.
How many A/D converter channels does the R5F564MFDDFB#31 provide, and what resolution options are available?
The R5F564MFDDFB#31 integrates two independent 12-bit A/D converters: S12AD unit 0 with 8 channels and unit 1 with 21 channels. Resolution is configurable per channel at 8-, 10-, or 12-bit modes, with conversion times of 0.42 µs (8-bit), 0.45 µs (10-bit), and 0.48 µs (12-bit) - all verified in Section 1.1 and Table 1.1 of R01DS0173EJ0120.
R5F564MFDDFB#31 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 144-LQFP
- Series:
- RX600
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- RXv2
- Core Size:
- 32-Bit Single-Core
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, SCI, SPI, SSI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 111
- Program Memory Size:
- 2MB (2M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 64K x 8
- RAM Size:
- 552K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 29x12b; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F564MFDDFB#31 FAQ
1.How can I place an order for R5F564MFDDFB#31 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F564MFDDFB#31 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F564MFDDFB#31 reliable?
The price and inventory of R5F564MFDDFB#31 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F564MFDDFB#31 is usually 5 days.
3.What payment methods are accepted for R5F564MFDDFB#31?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F564MFDDFB#31 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F564MFDDFB#31?
R5F564MFDDFB#31 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F564MFDDFB#31 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F564MFDDFB#31?
For technical support, including R5F564MFDDFB#31 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F564MFDDFB#31 requirements.
6.How does Aetrix verify that R5F564MFDDFB#31 is sourced from the original manufacturer or authorized distributors?
All R5F564MFDDFB#31 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F564MFDDFB#31 meets industry standards.
7.What is the process for return or replacement of R5F564MFDDFB#31?
All R5F564MFDDFB#31 units undergo pre-shipment inspection (PSI). If there is an issue with R5F564MFDDFB#31, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F564MFDDFB#31 part is unused and in its original packaging.
Return procedure for R5F564MFDDFB#31:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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