Renesas R5F564MFDDFP#31
- Part No.:
- R5F564MFDDFP#31
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 100-LQFP
- Datasheet:
-
R5F564MFDDFP#31.pdf
- Description:
- IC MCU 32BIT 2MB FLASH 100LFQFP
- Quantity:
- Payment:

- Shipping:

Inventory:2,023
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Product details
Overview
R5F564MFDDFP#31 from Renesas is a 32-bit RXv2 microcontroller targeting industrial Ethernet and USB-connected embedded systems, featuring 120 MHz operation (240 DMIPS), 4 MB on-chip code flash, 512 KB SRAM, IEEE 1588-compliant dual Ethernet MAC, full-speed USB 2.0 with battery charging support, and integrated 12-bit A/D and D/A converters.
For engineers reviewing the R5F564MFDDFP#31 datasheet, R5F564MFDDFP#31 pinout, R5F564MFDDFP#31 application, or R5F564MFDDFP#31 equivalent, key selection considerations include its 176-pin LFBGA package (PLQP0176KB-A), dual-channel Ethernet with PTP hardware acceleration, USBA module with 8.5 KB buffer, and support for IEC60730 functional safety compliance via built-in CRC, IWDTa, and self-diagnostic A/D features.
Technical Context
The R5F564MFDDFP#31 implements the RXv2 CPU core with single-precision IEEE-754 FPU, two multiply-accumulate units, and memory protection unit (MPU). It operates at up to 120 MHz with no-wait 4 MB flash and 512 KB SRAM, while supporting little- or big-endian data arrangement and variable-length instructions for compact code density.
Clock architecture includes independent PLL, HOCO/LOCO oscillators, and configurable peripheral clock domains (PCLKA up to 120 MHz for ETHERC/USBA/AES; PCLKB up to 60 MHz for timers and A/D). Power management provides four low-power modes and RTC battery backup via VBATT, with voltage monitoring across three LVD circuits.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit CISC Harvard architecture with 5-stage pipeline, 240 DMIPS @ 120 MHz |
| Flash Memory | 4 MB code flash with background programming/erasing (BGO) and no-wait access at 120 MHz |
| RAM | 512 KB SRAM (no wait states), 32 KB ECC RAM (SEC-DED), 8 KB standby RAM with deep software standby retention |
| Ethernet | Dual IEEE 1588-compliant MAC with MII/RMII, EPTPC hardware timestamping, and 3-channel EDMAC |
| USB | Full-speed USB 2.0 host/function with battery charging (USBA), 8.5 KB on-chip RAM buffer, OTG support |
| A/D Converter | Two 12-bit S12ADC units: Unit 0 (8 ch), Unit 1 (21 ch); conversion time 0.48 µs/channel at 12-bit resolution |
| Package | 176-pin LFBGA (PLQP0176KB-A), 24 × 24 mm, 0.5 mm pitch, –40°C to +85°C operating range (D-version) |
Pinout & Package
Package: PLQP0176KB-A - 176-pin Low-Profile Fine-Pitch Ball Grid Array, 24 mm × 24 mm, 0.5 mm ball pitch, RoHS-compliant, lead-free.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Power supply inputs | Core/analog power rails (2.7–3.6 V); separate analog domains enable noise isolation for ADC/DAC |
| VBATT | Battery backup supply | Enables RTC operation during main power loss; supports coin-cell or supercapacitor backup |
| XTAL / EXTAL | Main crystal oscillator interface | Supports 8–24 MHz external crystal for precise system timing and Ethernet synchronization |
| MDIO / MDC | PHY management interface | IEEE 802.3-compliant MDIO/MDC bus for configuring external Ethernet PHY devices |
| ETXD0–7 / ERXD0–7 | Ethernet MAC data bus | 8-bit parallel MII interface; supports RMII with reduced pin count when external PHY selected |
| USBDP / USBDM | USB 2.0 differential data pair | Full-speed (12 Mbps) differential signaling; integrated transceiver eliminates need for external PHY |
| AD0–20 | Analog input channels | 21-channel analog input for S12ADC Unit 1; includes dedicated sample-and-hold and disconnection detection |
| DA0 / DA1 | Digital-to-analog outputs | Two 12-bit buffered DAC outputs; selectable amplifier or direct output mode for sensor calibration or actuator control |
Key Features
| Feature | Design Value |
|---|---|
| IEEE 1588 Hardware Timestamping | EPTPC block delivers sub-microsecond precision time stamping for PTPv2 synchronization in industrial Ethernet networks |
| IEC60730 Safety Support | Integrated oscillation-stoppage detection, CRC calculator, IWDTa with window function, and A/D self-diagnostic reduce external safety component count |
| USB Battery Charging | USBA module supports BC1.2 and proprietary charging protocols without external charger IC, enabling standalone USB-powered devices |
| Event Link Controller (ELC) | 119 internal event signals routed without CPU intervention-e.g., TPU trigger → A/D start → DMA transfer → interrupt-reducing latency and firmware overhead |
| Quad SPI Interface | QSPI supports single/dual/quad I/O modes for high-throughput serial flash boot and firmware updates, with sequential execution and configurable clock polarity/phase |
Applications
| Industrial Ethernet Gateway | Smart Energy Metering |
|---|---|
Use Scenario: Protocol translation between Modbus TCP, EtherNet/IP, and fieldbus networks in factory automation. IC Role / Device Role / Timing Role: Dual Ethernet MAC handles concurrent traffic; EPTPC enables precise time-synchronized sampling of power quality metrics. Use Value: Hardware-accelerated PTP eliminates software timestamp jitter, meeting IEC 61850-9-3 Class C (≤1 µs sync accuracy) requirements. | Use Scenario: Revenue-grade electricity meter with harmonic analysis, tamper detection, and remote firmware update over cellular backhaul. IC Role / Device Role / Timing Role: S12ADC Unit 1 acquires 21-channel analog inputs (voltage, current, temperature); QSPI boots secure firmware from encrypted serial flash. Use Value: On-chip AES-256 and SHA-256 ensure firmware integrity; 12-bit ADC with self-diagnostic meets IEC 62053-22 Class 0.5S accuracy requirements. |
| USB-C Powered Industrial Controller | Real-Time Audio Processing Node |
Use Scenario: Compact PLC or motion controller powered and programmed via USB-C with battery charging capability. IC Role / Device Role / Timing Role: USBA module negotiates USB PD contract and supplies regulated 5 V to system; GPTA generates PWM for servo drive control. Use Value: Integrated battery charging circuitry removes need for discrete USB charger IC, reducing BOM cost and board area by >30%. | Use Scenario: Edge audio analytics node performing real-time noise cancellation and voice command recognition in HVAC or building security systems. IC Role / Device Role / Timing Role: SSI interfaces with MEMS microphone array; SRC resamples incoming audio to match DSP algorithm requirements. Use Value: Dedicated 32-bit stereo SRC with 8–48 kHz input/output flexibility enables adaptive sampling without external codec, lowering system latency to <500 µs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F565NEHDFP#30 | Same RX64M family, 176-pin LFBGA, but with 2.5 MB flash, 384 KB SRAM, and single Ethernet channel | Lacks second Ethernet MAC and EPTPC; suitable for cost-sensitive single-network edge nodes | Select when dual Ethernet and PTP are not required and BOM cost reduction is prioritized |
| R5F566TEHDFP#30 | RX66T group part: 160 MHz CPU, 2 MB flash, 384 KB SRAM, no Ethernet, enhanced motor control timers (GPTP) | Optimized for servo/inverter control with 3-phase PWM dead-time compensation; no USB battery charging or SDHI | Prefer for high-performance motor drives where real-time PWM precision outweighs connectivity needs |
Compared with R5F564MFDDFP#31, R5F565NEHDFP#30 reduces flash/SRAM and removes one Ethernet channel-ideal for simpler gateways-while R5F566TEHDFP#30 trades connectivity for deterministic motor control peripherals, making it unsuitable for networked sensing but superior for motion-critical applications.
Availability
R5F564MFDDFP#31 is available at Aetrix Electronics and suitable for industrial Ethernet gateways, smart energy meters, USB-C powered controllers, and real-time audio processing nodes requiring stable component supply across multi-year production cycles.
Supply support for R5F564MFDDFP#31 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader headquartered in Tokyo, Japan, delivering microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.
The RX64M Group is designed for high-integrity industrial connectivity applications demanding dual Ethernet, USB, safety certification support, and rich analog integration-all within a single-chip solution.
FAQ
What is the maximum operating frequency and performance rating of the R5F564MFDDFP#31?
The R5F564MFDDFP#31 operates at a maximum frequency of 120 MHz and delivers 240 DMIPS of processing performance. Its RXv2 CPU core includes a single-precision IEEE-754 floating-point unit, two multiply-accumulate units, and a 5-stage pipeline. This performance level enables real-time protocol stack execution-including TCP/IP, USB device/host, and CAN FD-without external co-processors. The R5F564MFDDFP#31 sustains this speed with zero-wait-state access to both 4 MB flash and 512 KB SRAM.
Does the R5F564MFDDFP#31 support IEEE 1588 Precision Time Protocol (PTP) hardware timestamping?
Yes, the R5F564MFDDFP#31 integrates a dedicated IEEE 1588-compliant PTP controller (EPTPC) linked directly to its dual Ethernet MAC (ETHERC). This hardware block captures transmit and receive timestamps with sub-microsecond resolution, independent of CPU load. It supports PTPv2 (IEEE 1588-2008) profiles including boundary clocks and transparent clocks, enabling synchronization accuracy compliant with IEC 61850-9-3 Class C in industrial Ethernet deployments. The R5F564MFDDFP#31 does not require external timestamping ICs.
What USB capabilities does the R5F564MFDDFP#31 provide, and does it support battery charging?
The R5F564MFDDFP#31 includes the USBA module-a full-speed USB 2.0 host/function controller with integrated transceiver and 8.5 KB on-chip RAM buffer. It supports OTG operation and battery charging per USB Battery Charging Specification Rev 1.2 (BC1.2), including DCP, CDP, and SDP detection. Unlike basic USB modules, USBA enables direct negotiation of charging current (up to 1.5 A) without external charger ICs. This functionality is exclusive to 176- and 177-pin RX64M variants-confirming R5F564MFDDFP#31's full support.
How does the R5F564MFDDFP#31 meet IEC 60730 Class B functional safety requirements?
The R5F564MFDDFP#31 includes multiple hardware features certified for IEC 60730 Class B compliance: oscillation-stoppage detection, hardware CRC calculator, independent watchdog timer (IWDTa) with window function, register write protection, and self-diagnostic A/D converter. These eliminate reliance on software-only checks. The A/D self-test generates internal reference voltages (VREFL0/VREFH0) to verify linearity and offset-critical for safety-critical sensor monitoring. All features are documented in Renesas' Functional Safety Manual R01UM0077EJ0200 for the RX64M Group, confirming R5F564MFDDFP#31's suitability for household appliance and industrial control applications.
What are the memory resources available on the R5F564MFDDFP#31, and how are they protected?
The R5F564MFDDFP#31 provides 4 MB of on-chip code flash with background programming/erasing (BGO), 64 KB of reprogrammable data flash (100,000 erase/write cycles), 512 KB of general SRAM (no wait states), 32 KB of ECC-protected RAM (SEC-DED), and 8 KB of standby RAM. Flash protection includes Trusted Memory (TM) blocks 8–9, preventing unauthorized read-out. SRAM ECC detects and corrects single-bit errors and detects double-bit errors. The R5F564MFDDFP#31 also supports memory protection unit (MPU) configuration to isolate privileged vs. user code and data spaces-enabling robust partitioning in RTOS environments.
R5F564MFDDFP#31 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 100-LQFP
- Series:
- RX600
- Packaging:
- Tray
- Product Status:
- Discontinued at Digi-Key
- Programmable:
- Not Verified
- Core Processor:
- RXv2
- Core Size:
- 32-Bit Single-Core
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, SCI, SPI, SSI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 78
- Program Memory Size:
- 2MB (2M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 64K x 8
- RAM Size:
- 552K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 22x12b; D/A 1x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F564MFDDFP#31 FAQ
1.How can I place an order for R5F564MFDDFP#31 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F564MFDDFP#31 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F564MFDDFP#31 reliable?
The price and inventory of R5F564MFDDFP#31 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F564MFDDFP#31 is usually 5 days.
3.What payment methods are accepted for R5F564MFDDFP#31?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F564MFDDFP#31 transactions.
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R5F564MFDDFP#31 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F564MFDDFP#31 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F564MFDDFP#31?
For technical support, including R5F564MFDDFP#31 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F564MFDDFP#31 requirements.
6.How does Aetrix verify that R5F564MFDDFP#31 is sourced from the original manufacturer or authorized distributors?
All R5F564MFDDFP#31 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F564MFDDFP#31 meets industry standards.
7.What is the process for return or replacement of R5F564MFDDFP#31?
All R5F564MFDDFP#31 units undergo pre-shipment inspection (PSI). If there is an issue with R5F564MFDDFP#31, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F564MFDDFP#31 part is unused and in its original packaging.
Return procedure for R5F564MFDDFP#31:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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