Renesas R5F564MFDGFC#V1
- Part No.:
- R5F564MFDGFC#V1
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 176-LQFP
- Datasheet:
-
R5F564MFDGFC#V1.pdf
- Description:
- RX64M 2MB, 512KB LQFP176 SDHI 10
- Quantity:
- Payment:

- Shipping:

Inventory:2,209
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Product details
Overview
R5F564MFDGFC#V1 from Renesas is a 32-bit RXv2 microcontroller designed for industrial and networked embedded systems requiring real-time Ethernet, USB, CAN, and secure firmware execution. It operates at 120 MHz (240 DMIPS), integrates 4 MB on-chip code flash, 512 KB SRAM, IEEE 1588-compliant dual Ethernet MAC, full-speed USB 2.0 with battery charging, triple CAN, and hardware AES/SHA encryption - deployed in motor control gateways and industrial IoT edge nodes.
For engineers reviewing the R5F564MFDGFC#V1 datasheet, R5F564MFDGFC#V1 pinout, R5F564MFDGFC#V1 application, or R5F564MFDGFC#V1 equivalent, key selection criteria include its 176-pin LFBGA package (PLQP0176KB-A), dual-channel Ethernet with PTP support, 12-bit dual A/D converter (29 total channels), 12-bit dual D/A converter, and IEC60730 safety features including self-diagnostic A/D, oscillation-stop detection, and register write protection.
Technical Context
The R5F564MFDGFC#V1 implements the RXv2 CPU core with Harvard architecture, 5-stage pipeline, and IEEE-754 single-precision FPU - enabling deterministic 120 MHz real-time control. Its clock system supports external crystal (8–24 MHz) + PLL, internal HOCO (16/18/20 MHz), and dedicated 120-kHz IWDT oscillator, with independent domain clocks (ICLK up to 120 MHz, PCLKA up to 120 MHz, PCLKB up to 60 MHz).
Peripheral integration includes dual ETHERC modules with EPTPC (IEEE 1588), EDMAC (3-channel DMA), USBA with 8.5 KB buffer and battery charging support, three CAN modules (32 mailboxes each), and S12ADC with dual units (8 + 21 channels), all coordinated via Event Link Controller (ELC) for CPU-offload event chaining without software intervention.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit CISC Harvard core with 5-stage pipeline, 240 DMIPS @ 120 MHz |
| Memory | 4 MB code flash (no wait states @ 120 MHz), 512 KB SRAM (no wait), 64 KB data flash (100k erase cycles) |
| Connectivity | Dual IEEE 1588 Ethernet MAC + EPTPC, full-speed USB 2.0 with battery charging (USBA), 3× CAN (ISO11898-1), 9× SCI/SCIg/h, 4× SCIFA, 2× RIIC, QSPI, SDHI |
| Analog Peripherals | Two 12-bit A/D converters (8 + 21 channels, 0.48 µs/ch), two 12-bit D/A converters, on-chip temperature sensor (±1°C) |
| Security & Safety | Hardware AES-128/192/256, DES/T-DES, SHA-1/224/256, IEC60730 compliance features: A/D self-test, oscillation-stop detection, CRC, IWDTa, register write protection |
| Package & Temp | 176-pin LFBGA (PLQP0176KB-A, 24 × 24 mm, 0.5 mm pitch), industrial grade (–40°C to +105°C, G-version) |
Pinout & Package
Package: PLQP0176KB-A - 176-pin Low-Profile Fine-Pitch Ball Grid Array (24 × 24 mm, 0.5 mm pitch), RoHS-compliant, lead-free, moisture sensitivity level 3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Power supply inputs | Separate digital (VCC) and analog (AVCC0/AVCC1) rails enable noise isolation for ADC/DAC operation |
| XTAL / EXTAL | Main crystal oscillator terminals | Supports 8–24 MHz external crystal for precise system clock generation and IEEE 1588 time synchronization |
| ETH_MDC / ETH_MDIO | MDIO management interface | Enables PHY configuration and status monitoring for both Ethernet channels without additional GPIO overhead |
| USB_VBUS / USB_DP / USB_DM | USB 2.0 physical interface | Full-speed USB transceiver with integrated VBUS sensing and battery charging detection per USB BC 1.2 spec |
| CAN0_TX / CAN0_RX | Channel 0 CAN differential pair | Direct connection to ISO11898-1 compliant transceiver; supports 32 mailbox filtering and loopback self-test |
| AD00–AD07 / AD10–AD120 | Analog input channels | Unit 0 (8 pins) and Unit 1 (21 pins) share dedicated sample-and-hold; disconnection detection prevents erroneous readings |
Key Features
| Feature | Design Value |
|---|---|
| Dual IEEE 1588 Ethernet with EPTPC | Hardware timestamping and PTP slave/master operation with sub-microsecond accuracy for synchronized industrial automation networks |
| USBA with battery charging | Integrated USB BC 1.2-compliant charging detection and power negotiation eliminates external charger IC in portable edge devices |
| IEC60730 Class B support | On-chip self-test routines (A/D, oscillator, memory CRC), register lock bits, and fault-detecting IWDT meet functional safety requirements for Class B appliances |
| Event Link Controller (ELC) | 119 internal event signals routed without CPU intervention - e.g., TPU output triggers A/D conversion or PWM dead-time adjustment |
| Trusted Memory (TM) function | Blocks 8 and 9 of code flash are read-protected, preventing unauthorized firmware extraction while allowing secure boot verification |
Applications
| Industrial Ethernet Gateway | Smart Motor Drive Controller |
|---|---|
Use Scenario: Aggregating Modbus TCP, CANopen, and EtherCAT fieldbus data into a unified 100 Mbps Ethernet backbone with precise time synchronization. IC Role / Device Role / Timing Role: Primary application processor executing real-time protocol stacks, managing dual Ethernet interfaces with IEEE 1588 PTP, and coordinating CAN-to-Ethernet bridging. Use Value: Sub-microsecond PTP timestamping and hardware-accelerated packet filtering reduce jitter and CPU load, enabling deterministic <100 µs cycle times in motion control networks. | Use Scenario: Closed-loop servo control for 3-phase BLDC/PMSM motors with position feedback, current sensing, and safety monitoring. IC Role / Device Role / Timing Role: Real-time motor control MCU generating complementary PWM waveforms (MTU3/GPT), sampling current/voltage via dual 12-bit ADCs, and enforcing functional safety via IEC60730 diagnostics. Use Value: Hardware dead-time insertion, synchronous PWM update, and on-chip temperature sensing enable safe, high-efficiency motor operation without external gate drivers or safety monitors. |
| Secure Industrial IoT Edge Node | USB-Enabled Human-Machine Interface (HMI) |
Use Scenario: Field-deployable edge node collecting sensor data, performing local AI inference, and securely transmitting encrypted telemetry over TLS via Ethernet or USB. IC Role / Device Role / Timing Role: Secure application host with hardware AES/SHA acceleration, trusted memory for firmware integrity, and dual Ethernet for redundant connectivity. Use Value: On-the-fly encryption/decryption of sensor payloads using dedicated crypto engines reduces latency and offloads ARM/RX cores, preserving bandwidth for real-time tasks. | Use Scenario: Touchscreen HMI panel connecting to PLCs via USB device mode while supporting firmware updates and battery charging via USB host mode. IC Role / Device Role / Timing Role: Dual-role USB controller (USBA) with integrated 8.5 KB buffer and BC 1.2 charging detection acting as both peripheral and host. Use Value: Eliminates need for separate USB PHY and charger IC, reducing BOM cost and PCB area while enabling seamless field updates and portable operation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F565NEDGFC#V1 | Same RX64M family, 176-pin LFBGA, but 2.5 MB flash, 384 KB SRAM, no USBA (USBb only), no SDHI | Lacks battery charging USB, SD host, and full crypto suite - suitable for cost-sensitive non-secure gateway designs | Select when USB battery charging, SD card logging, or AES/SHA acceleration are not required |
| R7FA6M2AF3CFB#AA0 | RX72M-based, 176-pin LQFP, 1.0 GHz CPU (ARM Cortex-M4F), 2 MB flash, 384 KB SRAM, single Ethernet, no USBA | Higher CPU throughput but lacks dual Ethernet, battery charging USB, and IEC60730-certified safety features | Prefer for compute-intensive vision/audio workloads where dual Ethernet and functional safety are secondary |
Compared with R5F565NEDGFC#V1 and R7FA6M2AF3CFB#AA0, the R5F564MFDGFC#V1 uniquely combines dual IEEE 1588 Ethernet, USBA with battery charging, full IEC60730 diagnostics, and 4 MB flash - making it optimal for safety-critical, time-synchronized industrial gateways requiring secure firmware and field-upgradable connectivity.
Availability
R5F564MFDGFC#V1 is available at Aetrix Electronics and suitable for industrial gateways, motor drive controllers, secure IoT edge nodes, and human-machine interfaces requiring stable component supply across extended product lifecycles.
Supply support for R5F564MFDGFC#V1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and enterprise applications.
The RX64M Group - including R5F564MFDGFC#V1 - was engineered for real-time industrial networking, integrating dual Ethernet, USB, CAN, and functional safety features to replace multi-chip solutions in programmable logic controllers and factory automation equipment.
FAQ
What is the maximum operating frequency and performance rating of the R5F564MFDGFC#V1?
The R5F564MFDGFC#V1 operates at a maximum frequency of 120 MHz and delivers 240 DMIPS of processing performance. Its RXv2 CPU core includes a single-precision IEEE-754 floating-point unit, 32-bit multiplier (1-cycle execution), and divider (2-cycle execution). This performance level enables real-time execution of industrial protocol stacks, motor control algorithms, and cryptographic operations without external co-processors - verified in the R01DS0173EJ0120 datasheet Section 1.1.
Does the R5F564MFDGFC#V1 support IEEE 1588 Precision Time Protocol (PTP)?
Yes, the R5F564MFDGFC#V1 integrates a dedicated PTP controller (EPTPC) linked to both Ethernet MAC channels, enabling hardware timestamping of PTP frames with sub-microsecond accuracy. It supports PTP slave and master modes, transparent clock functionality, and synchronization over standard Ethernet infrastructure - confirmed in Section 1.1 and Figure 1.1 of the R01DS0173EJ0120 datasheet.
What USB capabilities does the R5F564MFDGFC#V1 provide?
The R5F564MFDGFC#V1 includes the USBA module - a full-speed USB 2.0 host/function controller with battery charging (BC 1.2) support, 8.5 KB on-chip RAM buffer, and integrated transceiver. It supports OTG operation and eliminates need for external pull-up/pull-down resistors. This capability is exclusive to 176-pin RX64M variants like R5F564MFDGFC#V1 - detailed in Table 1.1 and Section 1.1 of R01DS0173EJ0120.
How many analog-to-digital converter (ADC) channels does the R5F564MFDGFC#V1 have, and what resolution options are supported?
The R5F564MFDGFC#V1 integrates two independent 12-bit A/D converters: S12ADC Unit 0 with 8 channels and Unit 1 with 21 channels (29 total). Resolution is configurable per channel at 8-, 10-, or 12-bit; conversion time is 0.42 µs (8-bit), 0.45 µs (10-bit), or 0.48 µs (12-bit). Both units support self-diagnostic voltage generation and analog input disconnection detection - specified in Section 1.1 and Table 1.1 of R01DS0173EJ0120.
Is the R5F564MFDGFC#V1 qualified for functional safety standards such as IEC60730?
Yes, the R5F564MFDGFC#V1 includes multiple hardware features certified for IEC60730 Class B compliance: oscillation-stoppage detection, frequency measurement circuitry, CRC calculation unit, independent watchdog timer (IWDTa), A/D converter self-diagnostic function, and register write protection. These are explicitly listed in the "Useful functions for IEC60730 compliance" section of the R01DS0173EJ0120 datasheet (Page 1).
R5F564MFDGFC#V1 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 176-LQFP
- Series:
- RX
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv2
- Core Size:
- 32-Bit
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, SCI, SPI, SSI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 127
- Program Memory Size:
- 2MB (2M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 64K x 8
- RAM Size:
- 512K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 29x12b; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F564MFDGFC#V1 FAQ
1.How can I place an order for R5F564MFDGFC#V1 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F564MFDGFC#V1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F564MFDGFC#V1 reliable?
The price and inventory of R5F564MFDGFC#V1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F564MFDGFC#V1 is usually 5 days.
3.What payment methods are accepted for R5F564MFDGFC#V1?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F564MFDGFC#V1 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F564MFDGFC#V1?
R5F564MFDGFC#V1 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F564MFDGFC#V1 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F564MFDGFC#V1?
For technical support, including R5F564MFDGFC#V1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F564MFDGFC#V1 requirements.
6.How does Aetrix verify that R5F564MFDGFC#V1 is sourced from the original manufacturer or authorized distributors?
All R5F564MFDGFC#V1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F564MFDGFC#V1 meets industry standards.
7.What is the process for return or replacement of R5F564MFDGFC#V1?
All R5F564MFDGFC#V1 units undergo pre-shipment inspection (PSI). If there is an issue with R5F564MFDGFC#V1, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F564MFDGFC#V1 part is unused and in its original packaging.
Return procedure for R5F564MFDGFC#V1:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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