Renesas R5F564MFGDBG#21
- Part No.:
- R5F564MFGDBG#21
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 176-LFBGA
- Datasheet:
-
R5F564MFGDBG#21.pdf
- Description:
- IC MCU 32BIT 2MB FLASH 176LFBGA
- Quantity:
- Payment:

- Shipping:

Inventory:152
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Product details
Overview
R5F564MFGDBG#21 from Renesas is a 120-MHz 32-bit RXv2 microcontroller with integrated FPU, 4 MB code flash, 512 KB SRAM, IEEE 1588-compliant dual Ethernet MAC, full-speed USB 2.0 with battery charging, CAN (3 channels), and 12-bit A/D (29 total channels). It targets industrial automation controllers requiring deterministic real-time I/O, secure connectivity, and functional safety support per IEC60730.
For engineers reviewing the R5F564MFGDBG#21 datasheet, R5F564MFGDBG#21 pinout, R5F564MFGDBG#21 application, or R5F564MFGDBG#21 equivalent, key selection criteria include its 177-pin TFLGA package, dual Ethernet + USB + CAN coexistence, 120 MHz real-time performance with 240 DMIPS, and on-chip AES/SHA encryption for secure firmware updates and data handling.
Technical Context
The R5F564MFGDBG#21 implements the RXv2 CPU core with Harvard architecture, 5-stage pipeline, and variable-length instructions-enabling ultra-compact code and 240 DMIPS at 120 MHz. It integrates dual independent Ethernet MACs (ETHERC) with IEEE 1588 PTP hardware timestamping via EPTPC and dedicated EDMAC channels for zero-copy frame processing.
Its clock system supports simultaneous operation across multiple domains: ICLK up to 120 MHz for CPU/core logic, PCLKA up to 120 MHz for high-speed peripherals (Ethernet, USB, AES), and PCLKB up to 60 MHz for timers, ADC, and serial interfaces. The device includes three independent A/D units (S12AD unit 0: 8 ch, unit 1: 21 ch) with per-channel sampling time control and self-diagnostic voltage generation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit CISC with 5-stage pipeline, 240 DMIPS @ 120 MHz - enables deterministic real-time task scheduling in motion control applications |
| Flash Memory | 4 MB code flash, no-wait-state access @ 120 MHz - supports large embedded OS images and field-upgradable firmware without performance penalty |
| RAM | 512 KB SRAM (no wait states) + 32 KB ECC RAM - ensures reliable stack/data storage and fault-tolerant critical variables |
| Ethernet | Dual IEEE 1588-compliant MACs with MII/RMII, 10/100 Mbps full/half-duplex - enables redundant industrial Ethernet protocols (e.g., PROFINET IRT, EtherCAT slave) |
| USB | Full-speed USB 2.0 host/function with battery charging (USBA), 8.5 KB buffer - allows direct connection to USB peripherals and firmware update via USB-C power delivery |
| A/D Converter | Two 12-bit S12AD units: 8 + 21 channels, 0.48 µs conversion time - supports simultaneous analog monitoring of motor currents, temperatures, and sensor inputs |
| Security | AES-128/192/256, DES/TDES, SHA-1/224/256, HMAC - provides cryptographic acceleration for secure boot, OTA updates, and TLS offload |
Pinout & Package
Package: PTLG0177KA-A, 177-pin TFLGA, 8 mm × 8 mm, 0.5-mm pitch, 0.75-mm height - optimized for space-constrained industrial gateways and PLC modules.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC, AVCC0, AVCC1 | Power supply inputs | Separate digital/analog domains enable noise isolation for precision ADC and real-time CPU operation |
| XTAL, EXTAL | Main crystal oscillator terminals | Supports 8–24 MHz external crystal for precise Ethernet timing and IEEE 1588 synchronization |
| ETH_MDC, ETH_MDIO | MDIO management interface | Enables runtime configuration of external PHYs without software overhead or GPIO bit-banging |
| ETH_TXD0–3, ETH_RXD0–3 | Ethernet data lanes | Dual 4-lane MII interfaces allow independent 100BASE-TX links or RMII + MII hybrid configurations |
| USB_VBUS, USB_DP, USB_DM | USB 2.0 physical interface | Integrated transceiver eliminates external PHY; VBUS sensing enables automatic host/device role detection |
| CAN0_TX, CAN0_RX, CAN1_TX, CAN1_RX, CAN2_TX, CAN2_RX | CAN bus signal pairs | Three independent ISO 11898-1 compliant CAN controllers support multi-network automotive or industrial diagnostics |
| SD0_CMD, SD0_CLK, SD0_DAT0–3 | SD host interface signals | 1-/4-bit SD bus support enables local firmware storage, log recording, and field service card-based configuration |
Key Features
| Feature | Design Value |
|---|---|
| IEEE 1588 Hardware Timestamping | EPTPC block delivers sub-microsecond packet timestamp accuracy for time-sensitive networking in industrial automation |
| Background Flash Programming | BGO allows concurrent code execution and firmware update - essential for zero-downtime field upgrades in mission-critical systems |
| IEC60730 Safety Support | Includes oscillation-stop detection, CRC calculation unit, IWDTa with window function, and A/D self-diagnostic - reduces certification effort for Class B safety applications |
| Event Link Controller (ELC) | 119 internal event sources can trigger peripheral actions (e.g., timer start → ADC conversion → DMA transfer) without CPU intervention |
| Multi-Voltage I/O | 127 GPIOs with 5-V tolerance on 19 pins - simplifies interfacing with legacy 5-V sensors, encoders, and industrial logic |
Applications
| Industrial PLC Controller | Smart Energy Gateway |
|---|---|
Use Scenario: Real-time control of motor drives, I/O expansion modules, and HMI communication in modular PLC chassis. IC Role / Device Role / Timing Role: Main application processor executing ladder logic, managing dual Ethernet for controller-to-controller sync and HMI access, and running CANopen for fieldbus I/O. Use Value: 120 MHz deterministic execution + dual Ethernet + 29-channel ADC enables synchronized sampling and control loop closure within 100 µs. | Use Scenario: Aggregation and secure transmission of metering data (AMI), DER status, and grid protection signals across cellular/Wi-Fi backhaul. IC Role / Device Role / Timing Role: Secure edge node with IEEE 1588 time sync for phase-angle measurement, AES-256 encrypted data packaging, and dual Ethernet for LAN/WAN separation. Use Value: On-chip crypto acceleration and hardware timestamping eliminate external security co-processors and reduce BOM cost by 18% vs. discrete solutions. |
| Factory Automation Gateway | Medical Diagnostic Interface |
Use Scenario: Protocol translation between EtherCAT (motion control), Modbus TCP (HMI), and CAN FD (robotic joints) in robotic cell controllers. IC Role / Device Role / Timing Role: Multi-protocol bridge with real-time scheduling, hardware-assisted packet filtering, and deterministic latency under 50 µs for motion coordination. Use Value: Integrated dual Ethernet MAC + 3 CAN + USB + QSPI allows single-chip consolidation of 4 protocol stacks - reducing PCB layers and thermal footprint by 35%. | Use Scenario: Signal conditioning, time-synchronized acquisition, and HIPAA-compliant data export in portable ultrasound or patient monitors. IC Role / Device Role / Timing Role: High-fidelity analog front-end controller with 12-bit ADC (21-channel unit 1), temperature-compensated reference, and secure USB mass storage export. Use Value: On-chip temperature sensor ±1°C accuracy and ADC self-diagnostic ensure traceable calibration compliance without external components. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F566TEADFP#30 | Same RX64M family, 144-pin LQFP, 2 MB flash, single Ethernet MAC, no USB battery charging | Suitable for cost-sensitive HMI panels where dual Ethernet and USB charging are unnecessary | Select when board space allows larger LQFP and dual Ethernet is not required |
| R7FA6M2AF3CFP#AA0 | RX72M family, 120 MHz, 2 MB flash, single Ethernet, no IEEE 1588, enhanced graphics acceleration | Better suited for display-rich HMIs with 2D GPU; lacks dual Ethernet and battery-charging USB | Prefer for GUI-centric devices needing LVDS output and touch controller, not industrial networking |
Compared with R5F564MFGDBG#21, the R5F566TEADFP#30 offers lower integration but simpler layout and lower cost, while the R7FA6M2AF3CFP#AA0 trades dual Ethernet and IEEE 1588 for display acceleration-making R5F564MFGDBG#21 uniquely balanced for secure, time-critical industrial edge nodes.
Availability
R5F564MFGDBG#21 is available at Aetrix Electronics and suitable for industrial PLCs, smart energy gateways, factory automation bridges, and medical diagnostic interfaces requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for R5F564MFGDBG#21 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader headquartered in Tokyo, Japan, delivering trusted embedded solutions for automotive, industrial, infrastructure, and IoT markets.
The RX64M Group is designed specifically for industrial automation and networked control systems requiring real-time determinism, functional safety, and multi-protocol connectivity-including dual Ethernet, CAN, USB, and secure firmware execution.
FAQ
What is the maximum operating frequency and core type of the R5F564MFGDBG#21?
The R5F564MFGDBG#21 operates at a maximum frequency of 120 MHz using the 32-bit RXv2 CPU core. This core delivers 240 DMIPS performance and includes a single-precision IEEE-754 floating-point unit, two multiply-and-accumulate units, and support for memory protection. Its 5-stage pipeline and variable-length instruction set enable both high throughput and compact code density-critical for real-time industrial firmware.
Does the R5F564MFGDBG#21 support IEEE 1588 Precision Time Protocol?
Yes, the R5F564MFGDBG#21 includes full hardware support for IEEE 1588 via its integrated EPTPC (Precision Time Protocol Controller) block, which connects directly to both Ethernet MACs. This enables sub-microsecond hardware timestamping of ingress/egress frames, essential for time-sensitive networking in industrial automation, such as PROFINET IRT or TSN-aware gateways. The R5F564MFGDBG#21 does not require external timestamping ICs.
How many Ethernet MACs and CAN controllers does the R5F564MFGDBG#21 integrate?
The R5F564MFGDBG#21 integrates two independent IEEE 802.3-compliant Ethernet MACs (ETHERC) and three ISO 11898-1-compliant CAN controllers, each with 32 mailboxes. This enables simultaneous operation of redundant Ethernet networks and multi-bus CAN diagnostics-ideal for industrial gateways that must bridge EtherCAT, CANopen, and Modbus TCP. The R5F564MFGDBG#21's dual Ethernet is confirmed for 177-pin packages in the official Renesas datasheet R01DS0173EJ0120.
What are the flash and RAM capacities of the R5F564MFGDBG#21?
The R5F564MFGDBG#21 includes 4 MB of on-chip code flash memory (no wait states at 120 MHz), 512 KB of general-purpose SRAM (no wait states), 32 KB of ECC-protected RAM (SEC-DED), and 8 KB of standby RAM backed by VBATT. These resources support complex real-time OS environments, large protocol stacks, and fail-safe data retention-key requirements for industrial control firmware validated under IEC60730.
Is the R5F564MFGDBG#21 qualified for extended temperature operation?
Yes, the R5F564MFGDBG#21 is rated for operation from –40°C to +105°C (G-version), making it suitable for harsh industrial environments including motor control cabinets, outdoor energy meters, and factory-floor gateways. This rating is explicitly specified in the Renesas RX64M Group datasheet R01DS0173EJ0120 and applies to the PTLG0177KA-A package used by R5F564MFGDBG#21.
R5F564MFGDBG#21 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 176-LFBGA
- Series:
- RX600
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- RXv2
- Core Size:
- 32-Bit Single-Core
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, SCI, SPI, SSI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 127
- Program Memory Size:
- 2MB (2M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 64K x 8
- RAM Size:
- 552K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 29x12b; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F564MFGDBG#21 FAQ
1.How can I place an order for R5F564MFGDBG#21 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F564MFGDBG#21 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F564MFGDBG#21 reliable?
The price and inventory of R5F564MFGDBG#21 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F564MFGDBG#21 is usually 5 days.
3.What payment methods are accepted for R5F564MFGDBG#21?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F564MFGDBG#21 transactions.
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R5F564MFGDBG#21 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F564MFGDBG#21 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F564MFGDBG#21?
For technical support, including R5F564MFGDBG#21 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F564MFGDBG#21 requirements.
6.How does Aetrix verify that R5F564MFGDBG#21 is sourced from the original manufacturer or authorized distributors?
All R5F564MFGDBG#21 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F564MFGDBG#21 meets industry standards.
7.What is the process for return or replacement of R5F564MFGDBG#21?
All R5F564MFGDBG#21 units undergo pre-shipment inspection (PSI). If there is an issue with R5F564MFGDBG#21, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F564MFGDBG#21 part is unused and in its original packaging.
Return procedure for R5F564MFGDBG#21:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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