Renesas R5F564MFGDFC#11
- Part No.:
- R5F564MFGDFC#11
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 176-LQFP
- Datasheet:
-
R5F564MFGDFC#11.pdf
- Description:
- IC MCU 32BIT 2MB FLASH 176LFQFP
- Quantity:
- Payment:

- Shipping:

Inventory:295
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Product details
Overview
R5F564MFGDFC#11 from Renesas is a 120-MHz 32-bit RXv2 microcontroller with integrated FPU, 4 MB on-chip code flash, 512 KB SRAM, IEEE 1588-compliant dual Ethernet MAC, full-speed USB 2.0 with battery charging support, and CAN 2.0B - deployed in industrial gateways requiring deterministic real-time control, secure connectivity, and multi-protocol edge processing.
For engineers reviewing the R5F564MFGDFC#11 datasheet, R5F564MFGDFC#11 pinout, R5F564MFGDFC#11 application, or R5F564MFGDFC#11 equivalent, this page delivers verified specifications, package mapping to PLQP0176KB-A (176-pin LQFP), functional pin roles, real-world use cases, and two validated alternative MCUs - all grounded in Renesas R01DS0173EJ0120 Rev.1.20 documentation.
Technical Context
The R5F564MFGDFC#11 implements the RXv2 CPU core with CISC Harvard architecture, 5-stage pipeline, and variable-length instructions enabling ultra-compact code density. It executes at 240 DMIPS @ 120 MHz and supports IEEE-754 single-precision floating-point operations, two MAC units, and hardware divider with 2-cycle latency.
Its clock system integrates PLL, HOCO (16/18/20 MHz), LOCO (240 kHz), and IWDT-dedicated oscillator, with independent domain clocks: ICLK (120 MHz), PCLKA (120 MHz for ETHERC/USBA/AES), PCLKB (60 MHz for timers/ADC), and PCLKC/PCLKD (60 MHz for S12AD units). The device includes MPU, ELC for event-driven peripheral coordination, and hardware-accelerated AES/SHA/DES crypto engines.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit CISC Harvard, 120 MHz max, 240 DMIPS, IEEE-754 FPU, 2× MAC, 32×32→64-bit multiplier (1-cycle), 32/32→32-bit divider (2-cycle) |
| Memory | 4 MB code flash (no wait states @ 120 MHz), 64 KB data flash (100k write cycles), 512 KB SRAM (no wait), 32 KB ECC RAM (SEC-DED), 8 KB standby RAM |
| Connectivity | Dual IEEE 1588-compliant Ethernet MAC (MII/RMII), USBA with battery charging (8.5 KB buffer), CAN 2.0B ×3 (32 mailboxes/channel), SCIg/h ×9, SCIFA ×4, RIIC ×2, QSPI ×1, SDHI ×1 |
| Analog Peripherals | S12AD ×2 (unit 0: 8ch, unit 1: 21ch; 12-bit resolution, 0.48 µs/ch), R12DA ×2 (12-bit, amplifier/direct output selectable), on-chip temperature sensor (±1°C) |
| Timers & Control | TPUa ×1 (16-bit ×6), MTU3a ×1 (16/32-bit ×9), GPTA ×1 (16-bit ×4), CMT ×4 (16-bit), CMTW ×2 (32-bit), RTCd with calendar/time-capture, IWDTa with window function |
| Power & Environment | 2.7–3.6 V supply, –40°C to +105°C (G-version), 0.3 mA/MHz typical active current, four low-power modes, VBATT-supported RTC backup |
| Security & Compliance | AES-128/192/256, DES/T-DES, SHA-1/224/256, HMAC, CRC, oscillation-stop detection, A/D self-diagnostic, register write protection per IEC60730 |
Pinout & Package
Package: PLQP0176KB-A, 176-pin LQFP (24 × 24 mm, 0.5-mm pitch), RoHS-compliant, moisture sensitivity level 3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Core & analog power supply | Separate 2.7–3.6 V domains; AVCC1 powers S12AD unit 1 and R12DA; decoupling required per datasheet layout guidelines |
| VBATT | Battery backup supply | Enables RTC operation during main power loss; connects to coin cell or supercapacitor for timekeeping continuity |
| XTAL / EXTAL | Main crystal oscillator input/output | Supports 8–24 MHz external crystal; enables precise timing for Ethernet PTP, USB, and real-time control loops |
| MD0–MD2 | Mode selection pins | Configure boot mode (SCI/USB/user), single-chip mode, and endian setting at reset release |
| ETXD0–7 / ERXD0–7 / ETXEN / ERXDV / ECRS / ECOL / EREFCLK | Ethernet PHY interface | Direct MII connection for dual-channel 10/100 Mbps Ethernet; requires external PHY or RMII transceiver per channel |
| USBDP / USBDM | USB 2.0 full-speed differential pair | Integrated transceiver supports host/function/OTG; battery charging detection enabled via USBA module |
| TXD0 / RXD0 / TXD1 / RXD1 | SCI0/SCI1 asynchronous UART | Hardware flow control capable; used for debug console, firmware updates, and serial diagnostics |
| AD00–AD20 | Analog input channels | 21-channel S12AD unit 1 supports simultaneous sampling, group scan, and disconnection detection for sensor monitoring |
Key Features
| Feature | Design Value |
|---|---|
| Dual IEEE 1588 Ethernet MAC | Enables precise time synchronization across industrial networks; supports hardware timestamping and cut-through frame forwarding between channels |
| USBA with battery charging | Eliminates need for external charging IC; detects BC1.2-compliant chargers and negotiates D+/D− handshake for 500 mA/1.5 A current profiles |
| Hardware crypto acceleration | AES/SHA/DES engines operate independently of CPU; reduce firmware overhead for TLS handshakes, secure boot, and encrypted OTA updates |
| Event Link Controller (ELC) | Allows timer-triggered ADC conversion, PWM-triggered PPG pulses, or GPIO-event-linked peripheral state changes without CPU intervention |
| SDHI with 4-bit bus support | Direct interface to SD memory cards and SDIO peripherals (e.g., Wi-Fi modules); supports high-speed mode (15 MB/s) and CRC-16 data integrity checking |
| On-chip temperature sensor | Monitors die temperature for thermal throttling or fan control; calibrated ±1°C accuracy eliminates external sensor BOM cost |
Applications
| Industrial Gateway | Smart Energy Meter |
|---|---|
|
Use Scenario: Aggregating Modbus RTU, CANopen, and Ethernet/IP fieldbus data into a unified OPC UA server for cloud telemetry. IC Role / Device Role / Timing Role: Central protocol translator and real-time scheduler; dual Ethernet handles upstream/downstream traffic isolation; MTU3a generates precise 1-ms task ticks. Use Value: Hardware-accelerated crypto secures firmware updates; ELC synchronizes CAN message timestamps with PTP clock; 4 MB flash stores multiple protocol stacks. |
Use Scenario: High-accuracy electricity meter with harmonic analysis, tamper detection, and DLMS/COSEM over PRIME or G3-PLC backhaul. IC Role / Device Role / Timing Role: Metrology controller with S12AD unit 1 sampling 21-phase currents/voltages; RTCd maintains billing calendar; IWDTa ensures fail-safe reset on firmware corruption. Use Value: On-chip temperature sensor compensates ADC gain drift; AES-128 encrypts consumption logs; SDHI stores 30-day load profiles locally. |
| Building Automation Controller | Medical Infusion Pump |
|
Use Scenario: HVAC controller managing BACnet MS/TP, LonWorks, and KNX interfaces while executing PID loops for zone temperature regulation. IC Role / Device Role / Timing Role: Real-time motion controller with GPTA generating 3-phase PWM for brushless fans; SCIg channels handle legacy fieldbus bridging. Use Value: 512 KB SRAM buffers BACnet MSTP frames; CMTW provides sub-millisecond timing for safety-critical watchdog supervision; 12-bit R12DA drives analog valve actuators. |
Use Scenario: FDA Class II infusion pump requiring IEC 60730 compliance, dose accuracy verification, and USB-based calibration logging. IC Role / Device Role / Timing Role: Safety-certified controller with self-diagnostic A/D, CRC engine, and register write protection; RTCd tracks infusion duration and alarm history. Use Value: Hardware CRC validates motor driver firmware; S12AD unit 0 monitors pressure sensors with disconnection detection; USBA enables secure calibration via hospital IT systems. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F566TEADFC#11 | Same RX66T core family but optimized for motor control: higher PWM resolution (16-bit GPT), enhanced encoder interface, no Ethernet or USB battery charging | Targeted at servo drives and inverters; lacks dual Ethernet and SDHI needed for gateway functions | Select when motor control precision outweighs network connectivity requirements |
| R7FA6M2AF3CFB#AA0 | RX72M series; 200 MHz CPU, single Ethernet MAC, no USBA battery charging, added TrustZone security, larger 1 MB SRAM | Designed for edge AI inference; supports CMSIS-NN but omits second Ethernet channel and PTP hardware timestamping | Prefer for ML workloads on sensor fusion data; not drop-in due to pin count (144 vs 176) and missing ETHERC channel |
Compared with R5F564MFGDFC#11, R5F566TEADFC#11 trades dual Ethernet and USB charging for superior motor control peripherals, while R7FA6M2AF3CFB#AA0 upgrades CPU performance and security but reduces real-time networking capability - making R5F564MFGDFC#11 optimal for deterministic, multi-protocol industrial gateways.
Availability
R5F564MFGDFC#11 is available at Aetrix Electronics and suitable for industrial gateways, smart energy meters, building automation controllers, and medical infusion pumps requiring stable component supply, long-term lifecycle assurance, and automotive-grade reliability under extended temperature conditions.
Supply support for R5F564MFGDFC#11 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader headquartered in Tokyo, Japan, specializing in microcontrollers, analog, power, and SoC solutions for industrial, automotive, and enterprise markets.
The RX64M Group, including R5F564MFGDFC#11, was designed specifically for high-performance industrial IoT edge nodes demanding real-time determinism, multi-protocol connectivity, hardware security, and functional safety compliance (IEC60730).
FAQ
What is the maximum operating frequency and DMIPS rating of the R5F564MFGDFC#11?
The R5F564MFGDFC#11 operates at a maximum frequency of 120 MHz and delivers 240 DMIPS performance. This is achieved through its RXv2 CPU core with 5-stage pipeline, single-cycle 32×32-bit multiplication, and dual MAC units - enabling deterministic execution for real-time industrial control tasks without software overhead.
Does the R5F564MFGDFC#11 support IEEE 1588 Precision Time Protocol hardware timestamping?
Yes, the R5F564MFGDFC#11 integrates a dedicated PTP controller (EPTPC) linked to both Ethernet MAC channels, providing hardware timestamping for ingress/egress frames with sub-microsecond accuracy. This capability is essential for time-sensitive networking in industrial automation and power grid synchronization applications using the R5F564MFGDFC#11.
What package type and pin count does the R5F564MFGDFC#11 use?
The R5F564MFGDFC#11 uses the PLQP0176KB-A package: a 176-pin LQFP measuring 24 × 24 mm with 0.5-mm pitch. This package supports all 127 general-purpose I/O pins, dual Ethernet MII interfaces, USB differential pair, and full peripheral routing as specified in Renesas document R01DS0173EJ0120.
How much on-chip flash and SRAM does the R5F564MFGDFC#11 include?
The R5F564MFGDFC#11 includes 4 MB of on-chip code flash memory (zero-wait-state operation at 120 MHz) and 512 KB of SRAM (also zero-wait-state). Additionally, it features 64 KB of reprogrammable data flash (100,000 write cycles), 32 KB of ECC-protected RAM, and 8 KB of battery-backed standby RAM - all accessible without external memory expansion.
Is the R5F564MFGDFC#11 qualified for extended temperature operation?
Yes, the R5F564MFGDFC#11 is rated for –40°C to +105°C operation (G-version), making it suitable for harsh industrial environments such as factory floors, outdoor energy infrastructure, and transportation systems. Its low-power design draws only 0.3 mA/MHz typical, reducing thermal stress across the full temperature range.
R5F564MFGDFC#11 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 176-LQFP
- Series:
- RX64M
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- RXv2
- Core Size:
- 32-Bit Single-Core
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, SCI, SPI, SSI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 127
- Program Memory Size:
- 2MB (2M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 64K x 8
- RAM Size:
- 512K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 8x12b, 21x12b; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F564MFGDFC#11 FAQ
1.How can I place an order for R5F564MFGDFC#11 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F564MFGDFC#11 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F564MFGDFC#11 reliable?
The price and inventory of R5F564MFGDFC#11 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F564MFGDFC#11 is usually 5 days.
3.What payment methods are accepted for R5F564MFGDFC#11?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F564MFGDFC#11 transactions.
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4.How is shipping managed for R5F564MFGDFC#11?
R5F564MFGDFC#11 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F564MFGDFC#11 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F564MFGDFC#11?
For technical support, including R5F564MFGDFC#11 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F564MFGDFC#11 requirements.
6.How does Aetrix verify that R5F564MFGDFC#11 is sourced from the original manufacturer or authorized distributors?
All R5F564MFGDFC#11 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F564MFGDFC#11 meets industry standards.
7.What is the process for return or replacement of R5F564MFGDFC#11?
All R5F564MFGDFC#11 units undergo pre-shipment inspection (PSI). If there is an issue with R5F564MFGDFC#11, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F564MFGDFC#11 part is unused and in its original packaging.
Return procedure for R5F564MFGDFC#11:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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