Renesas R5F564MFGDLJ#21
- Part No.:
- R5F564MFGDLJ#21
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 100-TFLGA
- Datasheet:
-
R5F564MFGDLJ#21.pdf
- Description:
- IC MCU 32BIT 2MB FLASH 100TFLGA
- Quantity:
- Payment:

- Shipping:

Inventory:416
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Product details
Overview
R5F564MFGDLJ#21 from Renesas is a 120-MHz 32-bit RXv2 MCU with single-precision FPU, 4 MB on-chip code flash, 512 KB SRAM, IEEE 1588-compliant dual Ethernet MAC, full-speed USB 2.0 with battery charging, and CAN interface - deployed in industrial gateways requiring deterministic real-time control, secure connectivity, and multi-protocol edge processing.
For engineers reviewing the R5F564MFGDLJ#21 datasheet, R5F564MFGDLJ#21 pinout, R5F564MFGDLJ#21 application, or R5F564MFGDLJ#21 equivalent, key selection criteria include its 177-pin TFLGA package, dual Ethernet + USB + CAN coexistence, 12-bit dual A/D with self-diagnostic, 32 KB ECC RAM for safety-critical code, and IEC60730-ready features including oscillation-stop detection and CRC hardware.
Technical Context
The R5F564MFGDLJ#21 implements the RXv2 CPU core with 5-stage CISC Harvard pipeline, supporting 240 DMIPS at 120 MHz and IEEE-754 single-precision floating-point operations. It integrates dual independent clock domains: PCLKA (up to 120 MHz) for high-speed peripherals (ETHERC, USBA, AES), and PCLKB (up to 60 MHz) for timers, ADCs, and low-power modules.
Its peripheral architecture includes three dedicated DMA controllers - DMACA (8 channels), EXDMAC (2 channels), and EDMAC (3 channels for Ethernet/PTP) - enabling concurrent high-bandwidth transfers without CPU intervention. The ELC (Event Link Controller) supports 119 internal event signals, allowing timer-triggered ADC sampling, PWM dead-time compensation, and RTC time-capture on external events - all without software overhead.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit CISC Harvard, 120 MHz max, 240 DMIPS, IEEE-754 FPU |
| Memory | 4 MB code flash (no wait states), 64 KB data flash (100k erase cycles), 512 KB SRAM, 32 KB ECC RAM, 8 KB standby RAM |
| Connectivity | Dual IEEE 1588 Ethernet MAC, full-speed USB 2.0 with battery charging (USBA), 3× CAN (ISO 11898-1), 2× I²C (1 Mbps), 9× SCI, 4× SCIFA, QSPI, SDHI |
| Analog | Two 12-bit S12ADC units (8 + 21 ch), 2× 12-bit R12DA, on-chip temperature sensor (±1°C) |
| Timers & Control | TPUa (6 ch), MTU3a (9 ch), GPTA (4 ch), CMT/CMTW, IWDTa with window function, RTC with battery backup |
| Security & Safety | AES/DES/SHA crypto engine (optional), MPU, register write protection, IEC60730 compliance features (CRC, self-diagnostic ADC, oscillation-stop detection) |
| Package & Environment | PTLG0177KA-A 177-pin TFLGA (8 mm × 8 mm, 0.5 mm pitch), –40°C to +105°C (G-version) |
Pinout & Package
Package: PTLG0177KA-A - 177-pin Thin Fine-Pitch Land Grid Array (TFLGA), 8 mm × 8 mm body, 0.5 mm pitch, 0.75 mm height, RoHS-compliant, lead-free.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Power supply inputs | Separate digital/analog supplies enable noise isolation; AVCC1 powers ADC/DAC/temperature sensor |
| VBATT | Battery backup supply | Retains RTC operation during main power loss; supports calendar/time-capture retention |
| ETXD0–ETXD3 / ETXCK / ETXEN / ERXD0–ERXD3 / ERXDV / ERXCK | Ethernet PHY interface | Dual MII/RMII-capable pins support simultaneous 10/100 Mbps full/half-duplex operation per channel |
| USBDP / USBDM / USBID / VBUS | USB 2.0 FS transceiver | Integrated PHY with battery charging detection (BC1.2); no external resistors required |
| CANH / CANL (CH0–CH2) | CAN differential bus terminals | Three independent ISO 11898-1 compliant CAN controllers, each with 32 mailboxes for prioritized messaging |
| AD00–AD28 | Analog input channels | 29 total ADC inputs across two units; unit 1 supports 21-channel scan with group priority and disconnection detection |
| DA00 / DA01 | Digital-to-analog outputs | Two 12-bit voltage outputs configurable for amplifier-buffered or direct rail-to-rail output |
| IRQ0–IRQ15 | External interrupt inputs | 16 dedicated edge-sensitive pins with programmable polarity; support wake-up from all low-power modes |
Key Features
| Feature | Design Value |
|---|---|
| Dual IEEE 1588 Ethernet MAC | Enables precise time-synchronized industrial networking (sub-microsecond timestamping) with hardware-accelerated PTP frame handling via EPTPC |
| IEC60730 Safety Support | Hardware CRC generator, oscillator-stop detection, A/D self-diagnostic, register write protection - reduces certification effort for Class B appliance control |
| Event Link Controller (ELC) | Eliminates CPU polling by directly linking 119 internal events (e.g., TPU overflow → ADC start → DMA transfer → interrupt) |
| Background Operation (BGO) | Allows concurrent code flash/data flash programming/erasing while executing application code - critical for firmware-over-the-air updates |
| Secure Boot & Trusted Memory | TM function blocks read access to flash blocks 8–9; supports secure boot verification and encrypted firmware storage |
| Low-Power Flexibility | Four distinct low-power modes (Sleep, All-Module Stop, Software Standby, Deep Software Standby) with sub-μA RTC retention and fast wake-up (<;10 μs) |
Applications
| Industrial Ethernet Gateway | Smart Energy Metering Hub |
|---|---|
Use Scenario: Aggregating Modbus TCP, CANopen, and BACnet MS/TP traffic across factory floor devices into time-synchronized IEEE 1588 backbone. IC Role / Device Role / Timing Role: Primary controller running real-time OS; dual Ethernet handles protocol bridging and PTP grandmaster/slave timing; CAN interfaces legacy machinery. Use Value: Hardware timestamping eliminates software jitter; 4 MB flash stores multiple protocol stacks; ECC RAM ensures integrity of time-critical control logic. | Use Scenario: Multi-tariff electricity meter with tamper detection, remote firmware update, and secure HAN communication via USB/SD card. IC Role / Device Role / Timing Role: Main metering SoC managing metrology ADC, RTC calendar, crypto-secured firmware updates, and dual-interface HAN (USB + SDHI). Use Value: On-chip AES/SHA enables firmware signature verification; data flash endurance (100k cycles) supports daily log writes; battery-backed RTC maintains billing accuracy during outages. |
| Programmable Logic Controller (PLC) CPU Module | Medical Infusion Pump Controller |
Use Scenario: Compact DIN-rail PLC with integrated EtherCAT slave, CAN fieldbus, and analog I/O for motion control in packaging lines. IC Role / Device Role / Timing Role: Deterministic real-time controller executing ladder logic; MTU3/GPT generate precise PWM for servo drives; ELC synchronizes I/O sampling to motion profiles. Use Value: 120 MHz CPU + 240 DMIPS delivers <;100 μs scan times; 32 KB ECC RAM protects control state; dual Ethernet supports redundant ring topology. | Use Scenario: Battery-powered infusion pump requiring FDA Class II compliance, flow rate precision, and alarm response under low-power conditions. IC Role / Device Role / Timing Role: Safety-certified controller managing motor drivers, pressure sensors (via 12-bit ADC), temperature monitoring, and USB host for configuration. Use Value: IEC60730 features (self-test, register lock, CRC) reduce Class B validation burden; deep software standby draws <;1 μA while retaining RTC and alarm state. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F565NEDDFP#30 | Same RX65N Group; 100-pin LQFP, 2 MB flash, no Ethernet MAC, adds 2D graphics accelerator | Suitable for HMI-centric designs without industrial networking; lacks IEEE 1588 and dual Ethernet | Select when display rendering > network determinism; not drop-in due to pin count, package, and missing ETHERC/USBA |
| R7FA6M2AF3CFP#AA0 | RX72M Group; 176-pin LFBGA, 120 MHz, dual Ethernet + USB + CAN, but 2 MB flash, no data flash, no hardware crypto | Targeted at cost-optimized industrial automation where AES/SHA not required and firmware update frequency is low | Choose for lower BOM cost where 2 MB flash suffices and cryptographic acceleration is unnecessary |
Compared with R5F564MFGDLJ#21, the R5F565NEDDFP#30 trades Ethernet and USB battery charging for graphics capability in smaller form factor, while the R7FA6M2AF3CFP#AA0 retains dual Ethernet and CAN but reduces memory and omits crypto - making R5F564MFGDLJ#21 optimal for secure, upgradable, time-synchronized edge nodes demanding full peripheral integration.
Availability
R5F564MFGDLJ#21 is available at Aetrix Electronics and suitable for industrial gateways, smart energy meters, PLC CPU modules, and medical infusion pump controllers requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for R5F564MFGDLJ#21 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader headquartered in Tokyo, Japan, delivering microcontrollers, analog, power, and SoC solutions for automotive, industrial, infrastructure, and IoT markets.
The RX64M Group - including R5F564MFGDLJ#21 - was designed for high-performance, safety-aware industrial edge devices requiring deterministic real-time control, multi-protocol connectivity (Ethernet/USB/CAN), and hardware-assisted functional safety compliance.
FAQ
What is the maximum operating frequency and performance rating of the R5F564MFGDLJ#21?
The R5F564MFGDLJ#21 operates at a maximum frequency of 120 MHz and delivers 240 DMIPS (Dhrystone MIPS) performance. Its RXv2 CPU core includes a single-precision IEEE-754 floating-point unit, 32-bit multiplier (1-cycle execution), and divider (2-cycle execution), enabling efficient signal processing and control algorithms in real-time applications.
Does the R5F564MFGDLJ#21 support IEEE 1588 Precision Time Protocol?
Yes, the R5F564MFGDLJ#21 integrates a dedicated PTP controller (EPTPC) linked to both Ethernet MAC channels, providing hardware timestamping for IEEE 1588-2008 compliant time synchronization. This enables sub-microsecond accuracy in industrial automation networks without CPU overhead or software-based timestamping delays.
What are the memory resources available on the R5F564MFGDLJ#21?
The R5F564MFGDLJ#21 includes 4 MB of on-chip code flash memory (no wait states at 120 MHz), 64 KB of reprogrammable data flash (rated for 100,000 erase/write cycles), 512 KB of general-purpose SRAM, 32 KB of ECC-protected RAM, and 8 KB of battery-backed standby RAM - collectively supporting complex firmware, secure OTA updates, and safety-critical data retention.
Which communication interfaces does the R5F564MFGDLJ#21 support for industrial connectivity?
The R5F564MFGDLJ#21 supports dual IEEE 1588 Ethernet MAC, full-speed USB 2.0 with battery charging (USBA), three independent CAN 2.0B controllers (32 mailboxes each), two I²C interfaces (up to 1 Mbps), nine SCI channels, four SCIFA interfaces with 16-byte FIFOs, QSPI, SDHI, and RSPI - enabling seamless integration into heterogeneous industrial networks.
How does the R5F564MFGDLJ#21 meet IEC60730 Class B safety requirements?
The R5F564MFGDLJ#21 includes hardware features essential for IEC60730 Class B compliance: oscillation-stoppage detection, hardware CRC generator, self-diagnostic A/D converter, register write protection, and memory protection unit (MPU). These reduce software validation burden and support safe startup, runtime monitoring, and fault recovery in household and industrial appliances.
R5F564MFGDLJ#21 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 100-TFLGA
- Series:
- RX600
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- RXv2
- Core Size:
- 32-Bit Single-Core
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, SCI, SPI, SSI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 78
- Program Memory Size:
- 2MB (2M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 64K x 8
- RAM Size:
- 552K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 22x12b; D/A 1x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F564MFGDLJ#21 FAQ
1.How can I place an order for R5F564MFGDLJ#21 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F564MFGDLJ#21 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F564MFGDLJ#21 reliable?
The price and inventory of R5F564MFGDLJ#21 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F564MFGDLJ#21 is usually 5 days.
3.What payment methods are accepted for R5F564MFGDLJ#21?
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R5F564MFGDLJ#21 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F564MFGDLJ#21 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F564MFGDLJ#21?
For technical support, including R5F564MFGDLJ#21 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F564MFGDLJ#21 requirements.
6.How does Aetrix verify that R5F564MFGDLJ#21 is sourced from the original manufacturer or authorized distributors?
All R5F564MFGDLJ#21 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F564MFGDLJ#21 meets industry standards.
7.What is the process for return or replacement of R5F564MFGDLJ#21?
All R5F564MFGDLJ#21 units undergo pre-shipment inspection (PSI). If there is an issue with R5F564MFGDLJ#21, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F564MFGDLJ#21 part is unused and in its original packaging.
Return procedure for R5F564MFGDLJ#21:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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