Renesas R5F564MFHDLC#21
- Part No.:
- R5F564MFHDLC#21
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 177-TFLGA
- Datasheet:
-
R5F564MFHDLC#21.pdf
- Description:
- IC MCU 32BIT 2MB FLASH 177TFLGA
- Quantity:
- Payment:

- Shipping:

Inventory:319
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Product details
Overview
R5F564MFHDLC#21 from Renesas is a 120-MHz 32-bit RXv2 microcontroller with single-precision IEEE-754 FPU, 4 MB on-chip code flash, 512 KB SRAM (no wait states), and integrated IEEE 1588-compliant Ethernet MAC - designed for industrial real-time control, networked HMI, and secure edge node applications requiring deterministic timing and dual CAN/USB/Ethernet connectivity.
For engineers reviewing the R5F564MFHDLC#21 datasheet, R5F564MFHDLC#21 pinout, R5F564MFHDLC#21 application, or R5F564MFHDLC#21 equivalent, this MCU delivers verified 240 DMIPS performance, hardware-accelerated AES/SHA encryption, 12-bit dual A/D converters (29 total channels), and full-speed USB 2.0 with battery charging support - all in a 176-pin LFBGA package rated for –40°C to +85°C operation.
Technical Context
The R5F564MFHDLC#21 implements the RXv2 CPU core with CISC Harvard architecture, 5-stage pipeline, and variable-length instructions enabling ultra-compact code density. It integrates dual clock domains: ICLK up to 120 MHz for CPU/core logic, and PCLKA/PCLKB up to 120/60 MHz respectively for peripheral modules including ETHERC, USBA, and S12AD.
Its memory subsystem includes 4 MB code flash (120-MHz zero-wait access), 64 KB data flash (100,000 write cycles), 512 KB SRAM, 32 KB ECC-protected RAM (SEC-DED), and 8 KB standby RAM backed by VBATT. Peripheral integration features dual Ethernet MACs with EPTPC (IEEE 1588), three CAN modules (32 mailboxes each), and two USB 2.0 FS interfaces - one with battery charging (USBA) and one standard (USBb).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit, 120 MHz max, 240 DMIPS, IEEE-754 single-precision FPU |
| Memory | 4 MB code flash (no wait states), 64 KB data flash, 512 KB SRAM, 32 KB ECC RAM |
| Connectivity | Dual IEEE 1588 Ethernet MAC, 3× CAN (ISO 11898-1), USBA + USBb, 2× RIIC, 4× SCIFA, QSPI, SDHI |
| Analog | Two 12-bit S12ADC units (8 + 21 channels), 2× R12DA, on-chip temperature sensor (±1°C) |
| Security | Optional AES-128/192/256, DES/TDES, SHA-1/224/256, HMAC, CRC, self-diagnostic A/D |
| Package & Temp | LFBGA-176 (PLQP0176KB-A, 24 × 24 mm, 0.5-mm pitch), –40°C to +85°C (D-version) |
| Power | 2.7–3.6 V supply, 0.3 mA/MHz typical active current, four low-power modes including deep software standby |
Pinout & Package
Package: PLQP0176KB-A - 176-pin Low-Profile Fine-Pitch Ball Grid Array (LFBGA), 24 mm × 24 mm, 0.5-mm ball pitch, RoHS-compliant, lead-free, moisture sensitivity level 3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Core & analog power supply | Separate 2.7–3.6 V domains for digital logic and analog peripherals; AVCC1 powers S12ADC unit 1 and R12DA |
| VBATT | Battery backup supply | Provides power to RTC and 8 KB standby RAM during main supply loss; enables calendar retention |
| RES# | Active-low reset input | Asynchronous hardware reset; initiates full system initialization including flash controller and clock recovery |
| CLKIN / CLKOUT | External crystal interface | Supports 8–24 MHz crystal/resonator for main clock oscillator; CLKOUT mirrors system clock for trace/debug |
| ETXD0–7 / ERXD0–7 | Ethernet PHY data bus | 8-bit parallel MII interface for first Ethernet channel; requires external PHY or RMII transceiver |
| USBDP / USBDM | USB 2.0 differential pair | Full-speed (12 Mbps) USB 2.0 interface for USBA module; integrated transceiver eliminates external PHY |
| CAN0TX / CAN0RX | CAN channel 0 signal pair | Dedicated differential I/O for ISO 11898-1 compliant CAN bus; supports 32 mailbox buffers and loopback test mode |
Key Features
| Feature | Design Value |
|---|---|
| IEEE 1588 Precision Time Protocol | Hardware timestamping engine (EPTPC) synchronized to dual Ethernet MACs for sub-microsecond time alignment in industrial automation |
| Background Operation (BGO) | Simultaneous code flash programming/erasing while executing application code - enables live firmware updates without interruption |
| Event Link Controller (ELC) | 119 internal event signals routed without CPU intervention - e.g., TPU capture triggers A/D conversion or sets GPIO state |
| Trusted Memory (TM) Protection | Blocks 8 and 9 of code flash are read-protected at hardware level - prevents extraction of critical boot or security routines |
| Self-Diagnostic A/D | On-chip voltage references (VREFL0/VREFH0, AVSS1/AVCC1) enable automatic calibration and fault detection without external components |
Applications
| Industrial Ethernet Gateway | Secure Edge Node Controller |
|---|---|
|
Use Scenario: Aggregating Modbus TCP, CANopen, and EtherCAT fieldbus data into a unified IEEE 1588-synchronized Ethernet backbone for PLC-to-cloud telemetry. IC Role / Device Role / Timing Role: Primary real-time controller with dual Ethernet MACs, hardware PTP timestamping, and deterministic interrupt latency (<1 µs jitter). Use Value: Eliminates need for external timing ICs or FPGA-based timestamping; reduces BOM cost by integrating 3× CAN, 2× USB, and crypto acceleration. |
Use Scenario: Embedded gateway in smart metering systems requiring tamper-resistant firmware updates, secure OTA patches, and local energy analytics. IC Role / Device Role / Timing Role: Root-of-trust execution environment with AES-256 encryption, SHA-256 signature verification, and trusted memory protection. Use Value: Meets IEC 62443-3-3 SL2 requirements via on-chip self-test, register write protection, and cryptographic key isolation. |
| Human-Machine Interface (HMI) | Networked Motor Drive Controller |
|
Use Scenario: 7-inch capacitive touchscreen HMI with local graphics rendering, SD card logging, and remote diagnostics over Ethernet/USB. IC Role / Device Role / Timing Role: Application processor with 512 KB zero-wait SRAM for frame buffer, SDHI for storage, and USBA for service port connectivity. Use Value: Enables high-refresh-rate UI rendering without external RAM; USB battery charging supports field-service tablet recharging. |
Use Scenario: Closed-loop servo drive controlling 3-phase PMSM motors with position feedback, current sensing, and safety monitoring. IC Role / Device Role / Timing Role: Real-time motion controller with MTU3/GPT PWM generation, 12-bit dual A/D for current sampling, and CAN for encoder feedback. Use Value: Achieves <1 µs PWM dead-time control accuracy and simultaneous 29-channel analog acquisition for multi-axis current/voltage monitoring. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F565NEHDFP#30 | Same RX64M family, 144-pin LQFP, 2.5 MB flash, 384 KB SRAM, no USBA (only USBb), single Ethernet MAC | Suitable for space-constrained designs where USB battery charging and dual Ethernet are not required | Select when lower pin count, smaller footprint, and reduced peripheral count meet functional requirements |
| R5F566TEHDFP#30 | RX66T family, 144-pin LQFP, 2.5 MB flash, 384 KB SRAM, 320 MHz CPU, enhanced motor control timers (MTU3+GPT), no Ethernet or USB | Optimized for high-performance motor control with advanced PWM synchronization and encoder interface | Prefer for servo/inverter applications demanding >300 MHz equivalent processing or dedicated motor timer blocks |
Compared with R5F564MFHDLC#21, the R5F565NEHDFP#30 offers identical architecture but reduced memory and connectivity - ideal for cost-sensitive industrial nodes; the R5F566TEHDFP#30 trades networking capability for higher CPU speed and motor-specific peripherals, making it unsuitable for Ethernet gateways but superior for real-time motor control loops.
Availability
R5F564MFHDLC#21 is available at Aetrix Electronics and suitable for industrial automation gateways, secure edge IoT nodes, human-machine interfaces, and networked motor drives requiring stable component supply across long production lifecycles.
Supply support for R5F564MFHDLC#21 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader delivering trusted embedded solutions for automotive, industrial, infrastructure, and IoT markets, with over 40 years of microcontroller innovation.
The RX64M Group - including R5F564MFHDLC#21 - was engineered for deterministic real-time control in networked industrial equipment, combining high-speed CPU performance, hardware security, and multi-protocol connectivity in a single chip.
FAQ
What is the maximum operating frequency and CPU architecture of the R5F564MFHDLC#21?
The R5F564MFHDLC#21 operates at a maximum frequency of 120 MHz using the 32-bit RXv2 CPU core. This core implements a CISC Harvard architecture with a 5-stage pipeline, variable-length instructions, and single-cycle 32×32-bit multiplication. It delivers 240 DMIPS and includes a single-precision IEEE-754 floating-point unit - all confirmed in the official R01DS0173EJ0120 datasheet Rev.1.20.
Does the R5F564MFHDLC#21 support IEEE 1588 Precision Time Protocol, and how is it implemented?
Yes, the R5F564MFHDLC#21 supports IEEE 1588 via its integrated EPTPC (PTP Controller for Ethernet) block, which is hardware-coupled to both Ethernet MACs. It provides hardware timestamping of ingress/egress frames with sub-microsecond resolution, independent of CPU load. The EPTPC supports PTP version 2 (IEEE 1588-2008) and operates synchronously with the Ethernet clock domain - details are specified on page 7 of the R01DS0173EJ0120 datasheet.
What are the flash and RAM capacities of the R5F564MFHDLC#21, and are they zero-wait-state?
The R5F564MFHDLC#21 integrates 4 MB of on-chip code flash memory and 512 KB of SRAM - both accessible at 120 MHz with zero wait states. It also includes 64 KB of reprogrammable data flash (100,000 write cycles) and 32 KB of ECC-protected RAM with SEC-DED error correction. These values are explicitly listed in Table 1.1 of the R01DS0173EJ0120 datasheet Rev.1.20.
Which communication interfaces does the R5F564MFHDLC#21 include for industrial networking?
The R5F564MFHDLC#21 includes dual IEEE 1588-compliant Ethernet MACs (ETHERC + EPTPC), three CAN 2.0B modules (32 mailboxes each), full-speed USB 2.0 with battery charging (USBA), standard USB 2.0 (USBb), four SCIFA UARTs with 16-byte FIFOs, two RIIC I²C interfaces (up to 1 Mbps), QSPI, SDHI, and RSPI. All are confirmed in the "Various communications interfaces" section of the R01DS0173EJ0120 datasheet.
Is the R5F564MFHDLC#21 qualified for extended temperature operation, and what is its package type?
Yes, the R5F564MFHDLC#21 is rated for –40°C to +85°C operation (D-version) and uses the PLQP0176KB-A package: a 176-pin LFBGA with 24 mm × 24 mm footprint and 0.5-mm ball pitch. This package is explicitly listed in the "Package Information" section of the R01DS0173EJ0120 datasheet Rev.1.20, page 1.
R5F564MFHDLC#21 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 177-TFLGA
- Series:
- RX600
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- RXv2
- Core Size:
- 32-Bit Single-Core
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, SCI, SPI, SSI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 127
- Program Memory Size:
- 2MB (2M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 64K x 8
- RAM Size:
- 552K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 29x12b; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F564MFHDLC#21 FAQ
1.How can I place an order for R5F564MFHDLC#21 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F564MFHDLC#21 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F564MFHDLC#21 reliable?
The price and inventory of R5F564MFHDLC#21 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F564MFHDLC#21 is usually 5 days.
3.What payment methods are accepted for R5F564MFHDLC#21?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F564MFHDLC#21 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F564MFHDLC#21?
R5F564MFHDLC#21 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F564MFHDLC#21 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F564MFHDLC#21?
For technical support, including R5F564MFHDLC#21 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F564MFHDLC#21 requirements.
6.How does Aetrix verify that R5F564MFHDLC#21 is sourced from the original manufacturer or authorized distributors?
All R5F564MFHDLC#21 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F564MFHDLC#21 meets industry standards.
7.What is the process for return or replacement of R5F564MFHDLC#21?
All R5F564MFHDLC#21 units undergo pre-shipment inspection (PSI). If there is an issue with R5F564MFHDLC#21, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F564MFHDLC#21 part is unused and in its original packaging.
Return procedure for R5F564MFHDLC#21:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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