Renesas R5F564MGCGFC#V1
- Part No.:
- R5F564MGCGFC#V1
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 176-LQFP
- Datasheet:
-
R5F564MGCGFC#V1.pdf
- Description:
- RX64M 2.5MB, 512KB LQFP176 120MH
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
R5F564MGCGFC#V1 from Renesas is a 120-MHz 32-bit RXv2 microcontroller with integrated FPU, 4-MB code flash, 512-KB SRAM, IEEE 1588-compliant dual Ethernet MAC, full-speed USB 2.0 with battery charging, CAN (3 channels), and 12-bit A/D (29 total channels). It targets industrial automation controllers requiring real-time deterministic communication, secure firmware updates, and high-precision analog sensing.
For engineers reviewing the R5F564MGCGFC#V1 datasheet, R5F564MGCGFC#V1 pinout, R5F564MGCGFC#V1 application, or R5F564MGCGFC#V1 equivalent, key selection criteria include its 176-pin LFBGA package (PLQP0176KB-A), dual Ethernet + PTP support, on-chip AES/SHA encryption, 32-KB ECC RAM for safety-critical data, and IEC60730 compliance features including self-diagnostic A/D and oscillation-stop detection.
Technical Context
The R5F564MGCGFC#V1 implements the RXv2 CPU core with CISC Harvard architecture, 5-stage pipeline, and variable-length instructions enabling ultra-compact code. It executes at 240 DMIPS @ 120 MHz and includes single-precision IEEE-754 FPU, two MAC units, and 32-bit multiplier with one-cycle latency.
Its clock system integrates PLL, HOCO (16/18/20 MHz), LOCO (240 kHz), and IWDT-dedicated oscillator. Peripheral clocks are independently configurable: PCLKA up to 120 MHz (for ETHERC, USBA, AES), PCLKB up to 60 MHz (for timers, UARTs), and dedicated ADCLKs for S12AD units - enabling precise timing isolation across mixed-criticality subsystems.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit, 120 MHz max, 240 DMIPS, IEEE-754 FPU, 72-bit accumulators |
| Memory | 4 MB code flash (no wait states @ 120 MHz), 64 KB data flash (100k erase cycles), 512 KB SRAM, 32 KB ECC RAM, 8 KB standby RAM |
| Connectivity | Dual IEEE 1588 Ethernet MAC (MII/RMII), USB 2.0 FS with battery charging (USBA), 3× CAN (ISO 11898-1), 9× SCI, 4× SCIFA, 2× RIIC, QSPI, SDHI |
| Analog | Two 12-bit A/D units (8 + 21 channels, 0.48 µs conversion), 2× 12-bit D/A, on-chip temperature sensor (±1°C) |
| Security & Safety | AES-128/192/256, DES/T-DES, SHA-1/224/256, HMAC, CRC, MPU, register write protection, IEC60730 self-test functions |
| Package & Temp | 176-pin LFBGA (PLQP0176KB-A, 24 × 24 mm, 0.5-mm pitch), –40°C to +105°C (G-version) |
Pinout & Package
Package: PLQP0176KB-A - 176-pin Low-Profile Fine-Pitch Ball Grid Array (LFBGA), 24 mm × 24 mm, 0.5-mm ball pitch, RoHS-compliant, lead-free.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Power supply inputs | Core (2.7–3.6 V), analog unit 0, analog unit 1 - independent filtering required per datasheet layout guidelines |
| VBATT | Battery backup supply | Enables RTC operation during main power loss; requires external coin cell or supercap |
| XTAL / EXTAL | Main crystal oscillator terminals | Supports 8–24 MHz external crystal; enables precise timing for Ethernet PTP and USB clock recovery |
| MD0 / MD1 | Mode setting pins | Determine boot mode (SCI/USB/user) and operating mode at reset release; must be pulled high/low per configuration |
| RES# | Active-low reset input | Asynchronous hardware reset; internal POR/LVD also generates reset when VCC drops below threshold |
| ETXD0–ETXD3 / ETXCK / ERXD0–ERXD3 / ERXCK | Ethernet PHY interface signals | Direct MII connection for channel 0; RMII shared with channel 1 via multiplexing - requires external PHY or integrated solution |
Key Features
| Feature | Design Value |
|---|---|
| Dual IEEE 1588 Ethernet MAC | Enables time-synchronized industrial networking (e.g., TSN-aware PLCs) with hardware timestamping and PTP event message handling |
| USB 2.0 FS with battery charging | Eliminates need for external charging IC in field-serviceable devices; supports BC1.2 compliant downstream port detection |
| IEC60730 Class B compliance support | Integrated oscillation-stop detection, CRC engine, A/D self-diagnostic, and register lock bits reduce certification effort for safety-critical firmware |
| 32-KB RAM with SEC-DED ECC | Protects critical control variables and stack against single-bit errors and detects double-bit faults - essential for SIL2/IEC61508 applications |
| Event Link Controller (ELC) | Hardware-triggered peripheral chaining (e.g., timer overflow → A/D start → DMA transfer) reduces CPU overhead and jitter in real-time loops |
Applications
| Industrial PLC Controller | Energy Meter with Secure Comms |
|---|---|
|
Use Scenario: Programmable logic controller executing ladder logic with synchronized I/O scanning and deterministic EtherCAT or PROFINET over Ethernet. IC Role / Device Role / Timing Role: Main application processor managing dual Ethernet interfaces, real-time task scheduling, encrypted firmware updates, and analog sensor acquisition. Use Value: Dual 1588 Ethernet enables sub-microsecond clock synchronization across distributed I/O modules without external grandmaster clocks. |
Use Scenario: Smart electricity meter supporting DLMS/COSEM over TCP/IP, remote firmware upgrades, and tamper-resistant data logging. IC Role / Device Role / Timing Role: Secure host MCU handling AES-encrypted communications, RTC-backed billing timestamps, and precision 12-bit A/D for current/voltage measurement. Use Value: On-chip AES/SHA and 32-KB ECC RAM meet IEC62056 and IEC61000-4-30 security requirements while reducing BOM cost vs. external crypto ICs. |
| Factory Automation Gateway | Medical Diagnostic Interface |
|
Use Scenario: Protocol gateway bridging CAN-based motor drives, USB-connected HMI panels, and Ethernet-based SCADA systems. IC Role / Device Role / Timing Role: Multi-protocol concentrator with concurrent CAN, USB, and dual Ethernet stacks, managed by RTOS with priority-based interrupt handling. Use Value: Integrated 3× CAN controllers and USB battery charging simplify connectivity to legacy equipment and service tools without external level shifters or chargers. |
Use Scenario: Portable ultrasound or patient monitor interfacing with CMOS image sensors, analog front-end, and wireless telemetry. IC Role / Device Role / Timing Role: High-integrity signal processor acquiring 12-bit ADC data, applying real-time DSP via FPU, and transmitting HIPAA-compliant data via encrypted USB/Ethernet. Use Value: Parallel Data Capture Unit (PDC) supports direct CMOS camera input; temperature sensor and self-diagnostic A/D ensure calibration traceability per IEC62304. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-performance industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F565NEHDFC#V0 | Same RX65N Group, 176-pin LFBGA, but 2-MB flash, no USBA module, single Ethernet MAC, no battery charging USB | Lacks dual Ethernet and USB battery charging; suitable for cost-sensitive gateways where PTP sync is not required | Select when BOM cost reduction is prioritized over time-synchronized networking and field-service USB charging |
| R7FA6M2AF3CFB#AA0 | RX72M Group, 176-pin LQFP, 100 MHz, 2-MB flash, single Ethernet, no USBA, enhanced functional safety (ASIL-B ready) | Optimized for automotive body electronics; includes ASIL-B diagnostic coverage not present in R5F564MGCGFC#V1 | Choose for automotive applications requiring ISO 26262 compliance; not drop-in due to different pinout and lower clock speed |
Compared with R5F564MGCGFC#V1, the R5F565NEHDFC#V0 trades dual Ethernet and USB battery charging for lower cost and smaller flash, while the R7FA6M2AF3CFB#AA0 shifts focus to automotive ASIL-B readiness at the expense of industrial PTP timing and USB charging capability - neither offers pin-to-pin compatibility.
Availability
R5F564MGCGFC#V1 is available at Aetrix Electronics and suitable for industrial automation controllers, smart energy meters, factory protocol gateways, and medical diagnostic interfaces requiring stable component supply across extended product lifecycles.
Supply support for R5F564MGCGFC#V1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for industrial, automotive, and enterprise applications.
The RX64M Group, including R5F564MGCGFC#V1, was designed for high-reliability industrial control systems demanding real-time Ethernet, functional safety support, and secure firmware execution in harsh environments.
FAQ
What is the maximum operating frequency and DMIPS rating of the R5F564MGCGFC#V1?
The R5F564MGCGFC#V1 operates at a maximum frequency of 120 MHz and delivers 240 DMIPS performance. This is achieved through its RXv2 CPU core with 5-stage pipeline, variable-length instruction set, and integrated single-cycle 32-bit multiplier. The DMIPS figure is measured under standard EEMBC CoreMark conditions and reflects real-world throughput for industrial control workloads running on R5F564MGCGFC#V1.
Does the R5F564MGCGFC#V1 support IEEE 1588 Precision Time Protocol?
Yes, the R5F564MGCGFC#V1 includes a dedicated PTP controller (EPTPC) tightly coupled to both Ethernet MACs, enabling hardware timestamping of PTP event messages with nanosecond-level accuracy. This allows R5F564MGCGFC#V1-based devices to function as transparent clocks or boundary clocks in time-sensitive networking applications without software timestamping overhead.
What are the memory resources available on the R5F564MGCGFC#V1?
The R5F564MGCGFC#V1 integrates 4 MB of on-chip code flash memory (with no wait states at 120 MHz), 64 KB of reprogrammable data flash (rated for 100,000 erase/write cycles), 512 KB of general-purpose SRAM, 32 KB of ECC-protected RAM (SEC-DED), and 8 KB of battery-backed standby RAM. All memory blocks are accessible via the 4-Gbyte linear address space of the RXv2 core.
Which package type and footprint does the R5F564MGCGFC#V1 use?
The R5F564MGCGFC#V1 uses the PLQP0176KB-A package: a 176-pin Low-Profile Fine-Pitch Ball Grid Array measuring 24 mm × 24 mm with 0.5-mm ball pitch. This LFBGA package supports high-density routing for industrial applications requiring multiple high-speed interfaces including dual Ethernet, USB, and CAN - and is compatible with standard PCB assembly processes.
What safety and security features does the R5F564MGCGFC#V1 provide for industrial applications?
The R5F564MGCGFC#V1 includes hardware-based security and safety features essential for industrial deployment: AES-128/192/256 and SHA-256 encryption engines, memory protection unit (MPU), register write protection, CRC calculation unit, oscillation-stop detection, and built-in self-test functions for the A/D converter. These capabilities directly support IEC60730 Class B compliance and secure firmware update workflows on R5F564MGCGFC#V1.
R5F564MGCGFC#V1 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 176-LQFP
- Series:
- RX
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv2
- Core Size:
- 32-Bit
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, SCI, SPI, SSI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 127
- Program Memory Size:
- 2.5MB (2.5M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 64K x 8
- RAM Size:
- 512K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 29x12b; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F564MGCGFC#V1 FAQ
1.How can I place an order for R5F564MGCGFC#V1 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F564MGCGFC#V1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F564MGCGFC#V1 reliable?
The price and inventory of R5F564MGCGFC#V1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F564MGCGFC#V1 is usually 5 days.
3.What payment methods are accepted for R5F564MGCGFC#V1?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F564MGCGFC#V1 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F564MGCGFC#V1?
R5F564MGCGFC#V1 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F564MGCGFC#V1 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F564MGCGFC#V1?
For technical support, including R5F564MGCGFC#V1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F564MGCGFC#V1 requirements.
6.How does Aetrix verify that R5F564MGCGFC#V1 is sourced from the original manufacturer or authorized distributors?
All R5F564MGCGFC#V1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F564MGCGFC#V1 meets industry standards.
7.What is the process for return or replacement of R5F564MGCGFC#V1?
All R5F564MGCGFC#V1 units undergo pre-shipment inspection (PSI). If there is an issue with R5F564MGCGFC#V1, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F564MGCGFC#V1 part is unused and in its original packaging.
Return procedure for R5F564MGCGFC#V1:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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