Renesas R5F564MGGDFB#31
- Part No.:
- R5F564MGGDFB#31
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 144-LQFP
- Datasheet:
-
R5F564MGGDFB#31.pdf
- Description:
- IC MCU 32BIT 2.5MB FLASH 144LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:2,412
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Product details
Overview
R5F564MGGDFB#31 from Renesas is a 32-bit RXv2 core microcontroller operating at up to 120 MHz (240 DMIPS), featuring 4 MB on-chip code flash, 512 KB SRAM, IEEE 1588-compliant dual Ethernet MAC, full-speed USB 2.0 with battery charging support, and integrated 12-bit A/D and D/A converters - deployed in industrial automation gateways requiring real-time control, secure connectivity, and deterministic timing.
For engineers reviewing the R5F564MGGDFB#31 datasheet, R5F564MGGDFB#31 pinout, R5F564MGGDFB#31 application, or R5F564MGGDFB#31 equivalent, key selection criteria include its 177-pin TFLGA package, dual-channel Ethernet with PTP, USB 2.0 FS host/function + battery charging capability, 120 MHz real-time performance with FPU, and IEC60730 safety features for certified embedded control systems.
Technical Context
The R5F564MGGDFB#31 implements the RXv2 CPU core with Harvard architecture, 5-stage pipeline, and variable-length instructions enabling ultra-compact code density. It integrates dual Ethernet controllers (ETHERC) with IEEE 1588 PTP support via EPTPC and dedicated EDMAC channels - one channel assigned to ETHERC and another to EPTPC - enabling hardware-accelerated timestamping and cut-through frame forwarding between ports.
Its clock system combines external crystal oscillation (8–24 MHz), internal HOCO (16/18/20 MHz), LOCO (240 kHz), and PLL-based frequency synthesis to drive ICLK at 120 MHz while independently configuring PCLKA (up to 120 MHz for high-speed peripherals), PCLKB (up to 60 MHz for timers and ADC), and ADCLK (up to 60 MHz per S12AD unit). The device supports four low-power modes and includes an independent watchdog timer (IWDTa) with window function and dedicated 120-kHz oscillator.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit CISC core with 5-stage pipeline, 240 DMIPS @ 120 MHz, IEEE-754 single-precision FPU, and memory protection unit (MPU) |
| Memory | 4 MB code flash (no wait states @ 120 MHz), 64 KB data flash (100,000 erase/write cycles), 512 KB SRAM (no wait), 32 KB ECC RAM, 8 KB standby RAM |
| Connectivity | Dual IEEE 1588-compliant Ethernet MAC (MII/RMII), USB 2.0 FS host/function with battery charging (USBA), 3× CAN (ISO11898-1), 9× SCIg/h, 4× SCIFA, 2× RIIC, QSPI, SDHI |
| Analog Peripherals | Two 12-bit A/D converters (8 + 21 channels), two 12-bit D/A converters, on-chip temperature sensor (±1°C), operational amplifier output option |
| Timers & Control | 29 extended-function timers including MTU3a (9 channels), GPTA (4×16-bit), TPUa (6×16-bit), CMT/CMTW, RTC with battery backup, IWDTa with window function |
| Package & Environment | 177-pin TFLGA (PTLG0177KA-A), 8 × 8 mm, 0.5-mm pitch, –40°C to +105°C (G-version), 2.7–3.6 V supply, 0.3 mA/MHz typical active current |
Pinout & Package
Package: PTLG0177KA-A, 177-pin Thin Fine-Pitch Land Grid Array (TFLGA), 8 mm × 8 mm, 0.5 mm pitch, 0.8 mm height, lead-free and RoHS compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC, AVCC0, AVCC1 | Power supply inputs | Core, analog domain 0, and analog domain 1 supplies (2.7–3.6 V); separate filtering required per domain for noise immunity |
| VBATT | Battery backup input | Supplies RTC during main power loss; enables calendar/clock retention without system reset |
| XTAL, EXTAL | Main crystal oscillator terminals | Supports 8–24 MHz external crystal for precise system clock generation and IEEE 1588 timebase stability |
| ETH_MDC, ETH_MDIO | MDIO management interface | Enables configuration and status polling of external PHY devices connected to dual Ethernet MACs |
| USB_VBUS, USB_DP, USB_DM | USB 2.0 physical layer interface | Full-speed USB transceiver with integrated battery charging detection (BC1.2 compliant) - requires no external pull-up resistors |
| SD0_CLK, SD0_CMD, SD0_DAT0–3 | SD host interface signals | 4-bit SD bus supporting SD memory and SDIO cards per SD Physical Layer Spec v3.01 (high-speed mode: 15 MB/s) |
Key Features
| Feature | Design Value |
|---|---|
| IEEE 1588 Precision Time Protocol | Hardware-accelerated timestamping via EPTPC block synchronized to dual Ethernet MACs - enables sub-microsecond clock synchronization in industrial Ethernet networks |
| USB Battery Charging Support | Integrated BC1.2 detection logic in USBA module eliminates need for external charger ID ICs - simplifies USB-powered gateway designs |
| IEC60730 Safety Compliance | On-chip oscillation-stoppage detection, CRC calculator, self-diagnostic A/D, register write protection, and IWDTa with window function - reduces external safety monitoring components |
| Event Link Controller (ELC) | 119 internal event signals routed without CPU intervention - enables deterministic peripheral chaining (e.g., timer-triggered A/D conversion → DMA transfer → interrupt) |
| Secure Cryptographic Acceleration | Optional AES-128/192/256, DES/T-DES, and SHA-1/224/256 engines - offloads encryption tasks from CPU for TLS/DTLS in edge IoT gateways |
Applications
| Industrial Ethernet Gateway | Smart Energy Metering Hub |
|---|---|
|
Use Scenario: Aggregating Modbus TCP, CANopen, and BACnet MS/TP traffic across factory floor devices into time-synchronized IEEE 1588 Ethernet backbone. IC Role / Device Role / Timing Role: Primary controller executing protocol translation, real-time packet timestamping, and deterministic scheduling via MTU3/GPT timers. Use Value: Dual Ethernet MAC + EPTPC delivers hardware PTP accuracy <1 µs, eliminating need for external time-sync ICs and reducing BOM cost by $1.20/unit. |
Use Scenario: Multi-tariff electricity meter collecting voltage/current samples via isolated ADCs, running DLMS/COSEM over IPv6, and reporting via cellular backhaul. IC Role / Device Role / Timing Role: Secure host processor managing encrypted metering data, RTC-backed billing intervals, and tamper-detection logic using IWDTa and LVD. Use Value: Integrated 12-bit A/D with self-diagnostic and 32 KB ECC RAM enable Class 0.5S metrology compliance without external calibration circuitry. |
| Building Automation Controller | Medical Infusion Pump Controller |
|
Use Scenario: HVAC zone controller interfacing with RS485 thermostats, DALI lighting drivers, and BACnet/IP network - requiring fail-safe operation and firmware updates over USB. IC Role / Device Role / Timing Role: Real-time scheduler coordinating PWM fan control, temperature sensing, and secure OTA updates via USB 2.0 with battery charging. Use Value: USBA module's integrated BC1.2 detection allows field technicians to update firmware using standard USB-C power banks - no proprietary chargers needed. |
Use Scenario: Life-critical infusion pump performing motor control, pressure sensing, and alarm logging under IEC 62304 Class C software requirements. IC Role / Device Role / Timing Role: Safety-certified MCU executing closed-loop PID control, real-time fault detection, and encrypted audit trail storage in data flash. Use Value: On-chip MPU, register write protection, and IEC60730-compliant self-test functions reduce functional safety certification effort by ~30% versus generic MCUs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F565NEDDFB#31 | Same RX65N Group platform but with 2 MB flash, 384 KB SRAM, single Ethernet MAC, no USB battery charging, and 144-pin LFBGA package | Suitable for cost-sensitive building controllers without dual-network redundancy or USB-powered field service | Select when dual Ethernet and USB BC1.2 are not required - saves $2.10/unit and reduces PCB area by 25% |
| R7FA6M2AF3CFB#AA0 | RX72M Group successor: 200 MHz CPU, single Ethernet + TSN support, enhanced security (TRNG, secure boot), 176-pin LQFP package | Targets next-gen IIoT edge AI inference nodes requiring higher throughput and hardware root-of-trust | Choose for new designs needing TSN time-aware shaping or PSA Level 2 certification - not drop-in compatible due to pinout and peripheral differences |
Compared with R5F564MGGDFB#31, R5F565NEDDFB#31 offers reduced memory and connectivity at lower cost for simpler gateways, while R7FA6M2AF3CFB#AA0 provides higher performance and advanced security for future-proofed edge deployments - neither matches the exact 177-pin TFLGA footprint or dual-PTP Ethernet capability of the R5F564MGGDFB#31.
Availability
R5F564MGGDFB#31 is available at Aetrix Electronics and suitable for industrial automation gateways, smart energy metering hubs, building automation controllers, and medical infusion pump controllers requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for R5F564MGGDFB#31 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and enterprise applications.
The RX64M Group, including R5F564MGGDFB#31, was designed for high-reliability industrial control systems demanding real-time determinism, functional safety compliance (IEC60730), and multi-protocol connectivity - especially where dual Ethernet with IEEE 1588 synchronization and secure USB device management are critical.
FAQ
What is the maximum operating frequency and CPU architecture of the R5F564MGGDFB#31?
The R5F564MGGDFB#31 operates at a maximum frequency of 120 MHz using the 32-bit RXv2 CPU core with Harvard architecture, 5-stage pipeline, and variable-length instruction set. It delivers 240 DMIPS performance and includes a single-precision IEEE-754 floating-point unit (FPU), on-chip multiplier (1-cycle execution), and divider (2-cycle execution). This architecture enables deterministic real-time response in industrial control applications where the R5F564MGGDFB#31 serves as the primary system controller.
Does the R5F564MGGDFB#31 support IEEE 1588 Precision Time Protocol, and how is it implemented?
Yes, the R5F564MGGDFB#31 supports IEEE 1588 through its integrated PTP controller for Ethernet (EPTPC), which is hardware-connected to both Ethernet MAC modules. Timestamping occurs at the physical layer with hardware capture of transmit/receive packet timestamps, enabling sub-microsecond synchronization accuracy. The R5F564MGGDFB#31 uses dedicated EDMAC channels - one for ETHERC and one for EPTPC - to offload timestamp processing from the CPU, making it suitable for time-critical industrial Ethernet applications.
What USB capabilities does the R5F564MGGDFB#31 provide, and is battery charging supported?
The R5F564MGGDFB#31 includes the USBA module, a full-speed USB 2.0 host/function controller with integrated battery charging (BC1.2) detection logic - available only on 176- and 177-pin packages like this part. It supports full-speed (12 Mbps) and low-speed (1.5 Mbps, host only) transfers, OTG operation, and incorporates 8.5 KB of on-chip RAM for endpoint buffering. No external pull-up/pull-down resistors are required. This makes the R5F564MGGDFB#31 ideal for field-serviceable gateways that accept firmware updates from USB power banks.
How many Ethernet MAC interfaces does the R5F564MGGDFB#31 integrate, and what PHY interfaces are supported?
The R5F564MGGDFB#31 integrates two independent IEEE 802.3-compliant Ethernet MAC controllers (ETHERC), each supporting 10/100 Mbps operation in full- or half-duplex mode. It supports both MII (Media Independent Interface) and RMII (Reduced MII) PHY connections, enabling flexible PHY selection. Each MAC has dedicated EDMAC channels and supports Magic Packet™ wake-on-LAN, IEEE 802.3x flow control, and multicast filtering - essential features for redundant industrial network topologies used by the R5F564MGGDFB#31.
What safety and reliability features make the R5F564MGGDFB#31 suitable for IEC60730-certified applications?
The R5F564MGGDFB#31 includes multiple IEC60730-compliant features: oscillation-stoppage detection, hardware CRC calculator, self-diagnostic A/D converter, register write protection, independent watchdog timer (IWDTa) with configurable window function, and memory protection unit (MPU). These features allow developers to meet Class B requirements without external safety monitors. The R5F564MGGDFB#31's design enables systematic fault coverage exceeding 90% - a key requirement for certified industrial control systems.
R5F564MGGDFB#31 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 144-LQFP
- Series:
- RX600
- Packaging:
- Tray
- Product Status:
- Discontinued at Digi-Key
- Programmable:
- Not Verified
- Core Processor:
- RXv2
- Core Size:
- 32-Bit Single-Core
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, SCI, SPI, SSI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 111
- Program Memory Size:
- 2.5MB (2.5M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 64K x 8
- RAM Size:
- 552K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 29x12b; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F564MGGDFB#31 FAQ
1.How can I place an order for R5F564MGGDFB#31 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F564MGGDFB#31 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F564MGGDFB#31 reliable?
The price and inventory of R5F564MGGDFB#31 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F564MGGDFB#31 is usually 5 days.
3.What payment methods are accepted for R5F564MGGDFB#31?
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R5F564MGGDFB#31 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F564MGGDFB#31 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F564MGGDFB#31?
For technical support, including R5F564MGGDFB#31 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F564MGGDFB#31 requirements.
6.How does Aetrix verify that R5F564MGGDFB#31 is sourced from the original manufacturer or authorized distributors?
All R5F564MGGDFB#31 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F564MGGDFB#31 meets industry standards.
7.What is the process for return or replacement of R5F564MGGDFB#31?
All R5F564MGGDFB#31 units undergo pre-shipment inspection (PSI). If there is an issue with R5F564MGGDFB#31, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F564MGGDFB#31 part is unused and in its original packaging.
Return procedure for R5F564MGGDFB#31:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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