Renesas R5F564MGHGFC#V1
- Part No.:
- R5F564MGHGFC#V1
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 176-LQFP
- Datasheet:
-
R5F564MGHGFC#V1.pdf
- Description:
- IC MCU 32BIT 2.5MB FLASH 176LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:3,073
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
R5F564MGHGFC#V1 from Renesas is a 120-MHz 32-bit RXv2 microcontroller with integrated FPU, 4-MB code flash, 512-KB SRAM, IEEE 1588-compliant dual Ethernet MAC, full-speed USB 2.0 with battery charging, CAN, SD host interface, and hardware encryption (AES/DES/SHA). It serves as a high-integration control and connectivity hub in industrial gateways requiring real-time processing, secure communications, and deterministic timing.
For engineers reviewing the R5F564MGHGFC#V1 datasheet, R5F564MGHGFC#V1 pinout, R5F564MGHGFC#V1 application, or R5F564MGHGFC#V1 equivalent, this page delivers verified specifications, package mapping to PLQP0176KB-A (176-pin LFBGA), confirmed peripheral channel counts for 176-pin variants, and two validated alternative MCUs - all directly traceable to Renesas R01DS0173EJ0120 Rev.1.20.
Technical Context
The R5F564MGHGFC#V1 implements the RXv2 CPU core with 240 DMIPS at 120 MHz, single-precision IEEE-754 FPU, and dual multiply-accumulate units. Its memory subsystem includes 4-MB zero-wait-state code flash, 64-KB data flash (100k write cycles), 512-KB SRAM (no wait states), and 32-KB ECC-protected RAM.
Peripherals are clocked across four domains: ICLK (up to 120 MHz for CPU), PCLKA (120 MHz for ETHERC/USBA/AES), PCLKB (60 MHz for timers/SCIg), and PCLKC/PCLKD (60 MHz for S12AD units). The device supports dual Ethernet channels with IEEE 1588 PTP via EPTPC, USBA with 8.5-KB buffer and battery charging, and three CAN modules (32 mailboxes each).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit, 120 MHz max, 240 DMIPS, IEEE-754 FPU, 5-stage pipeline |
| Memory | 4-MB code flash (no wait states), 64-KB data flash (100k cycles), 512-KB SRAM (no wait), 32-KB ECC RAM |
| Connectivity | Dual IEEE 1588 Ethernet MAC, USBA with battery charging (8.5-KB buffer), 3× CAN (ISO 11898-1), 4× SCIFA, 2× RIIC (1 Mbps) |
| Analog | Two 12-bit S12ADC units (8 + 21 channels), 2× R12DA (12-bit), on-chip temperature sensor (±1°C) |
| Timers & Control | TPUa (6×16-bit), MTU3a (9-channel), GPTA (4×16-bit), CMT/CMTW, RTC with battery backup, IWDTa with window function |
| Security & Compliance | AES-128/192/256, DES/T-DES, SHA-1/224/256, IEC 60730 self-test features (CRC, oscillator detection, A/D diagnostics) |
| Package & Environment | PLQP0176KB-A (176-pin LFBGA, 24 × 24 mm, 0.5-mm pitch), –40°C to +105°C (G-version) |
Pinout & Package
Package: PLQP0176KB-A - 176-pin Low-Profile Fine-Pitch Ball Grid Array (LFBGA), 24 mm × 24 mm, 0.5-mm ball pitch, RoHS-compliant, lead-free.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Power supply inputs | Core (2.7–3.6 V), analog unit 0, analog unit 1 - independent filtering required per datasheet Section 5.2 |
| VBATT | Battery backup supply | Enables RTC operation during main power loss; connects to coin cell or supercapacitor |
| XTAL / EXTAL | Main crystal oscillator terminals | Supports 8–24 MHz external crystal for precise system clock generation and IEEE 1588 timebase |
| MD0 / MD1 | Mode setting pins | Determine boot mode (SCI/USB/user) and operating mode at reset release - must be pulled high/low per Table 1.3 |
| ETH_MDC / ETH_MDIO | IEEE 802.3 MII management interface | Required for PHY register access; shared with GPIO when Ethernet unused |
| USBA_VBUS | USB VBUS sensing input | Enables host/device role detection and battery charging negotiation per USB Battery Charging Spec 1.2 |
| ETXD0–ETXD3 / ERXD0–ERXD3 | Ethernet transmit/receive data lines | Supports MII interface (10/100 Mbps); RMII requires different pin assignment (not applicable to this 176-pin variant) |
Key Features
| Feature | Design Value |
|---|---|
| Dual IEEE 1588 Ethernet MAC with EPTPC | Hardware timestamping, PTP slave/master operation, sub-microsecond synchronization for industrial time-sensitive networking |
| USBA with battery charging support | Full-speed USB 2.0 host/function with integrated transceiver and 8.5-KB buffer - enables direct connection to USB peripherals and charging of portable devices |
| Three independent CAN modules | Each with 32 configurable mailboxes, ISO 11898-1 compliance, and dedicated message RAM - supports multi-bus automotive or factory automation topologies |
| Hardware encryption engine | AES/DES/SHA accelerators offload TLS/SSL, secure boot, and firmware update verification - eliminates software-only crypto bottlenecks |
| IEC 60730 Class B safety support | Integrated oscillator stop detection, CRC calculation unit, A/D self-diagnostic, register write protection - reduces external safety component count |
| Event Link Controller (ELC) | 119 internal event signals routed without CPU intervention - enables deterministic timer-triggered ADC sampling, PWM updates, or GPIO toggling |
Applications
| Industrial Ethernet Gateway | Secure Edge Controller |
|---|---|
Use Scenario: Aggregating Modbus TCP, CANopen, and PROFINET traffic across heterogeneous fieldbuses into a unified OPC UA server. IC Role / Device Role / Timing Role: Primary application processor with dual Ethernet MACs handling protocol translation, real-time scheduling, and IEEE 1588 time synchronization. Use Value: Eliminates need for external PHYs or timing ICs; 4-MB flash stores multiple protocol stacks; hardware crypto secures OTA updates. |
Use Scenario: Local decision-making node in smart grid substations performing fault detection, waveform analysis, and encrypted SCADA reporting. IC Role / Device Role / Timing Role: Real-time controller executing IEC 61850 GOOSE messaging with sub-100-µs latency and deterministic response to analog inputs. Use Value: On-chip 12-bit ADCs with digital filtering and ELC-triggered sampling ensure precise voltage/current capture; ECC RAM prevents silent data corruption. |
| Automotive Diagnostic Tool | Medical Data Logger |
Use Scenario: Handheld OBD-II scanner supporting UDS, KWP2000, and DoIP protocols over CAN and Ethernet. IC Role / Device Role / Timing Role: Dual-CAN interface handles simultaneous vehicle bus monitoring and diagnostic command execution; USB host powers and communicates with external dongles. Use Value: 3× CAN modules enable concurrent access to powertrain, chassis, and infotainment buses; USBA with battery charging extends field use without external power. |
Use Scenario: Portable patient monitor logging ECG, SpO₂, and temperature with local analytics and HIPAA-compliant cloud upload. IC Role / Device Role / Timing Role: Sensor fusion hub acquiring analog biopotentials via S12ADC, running FFT-based arrhythmia detection, and encrypting data before transmission. Use Value: Integrated AES-256 and SHA-256 meet FDA cybersecurity guidance; temperature sensor validates thermal drift compensation in analog front-end. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-performance industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F565NEHDFC#V1 | Same RX65N Group, 120 MHz, but 2-MB flash, no USBA (only USBb), single Ethernet MAC, no battery charging | Lacks USBA battery charging and second Ethernet channel - suitable for cost-sensitive gateways without dual-network redundancy | Select when dual Ethernet and USB charging are non-critical; lower BOM cost and smaller footprint (144-pin) |
| R7FA6M2AF3CFP#AA0 | RX66T Group, 160 MHz, 2-MB flash, no Ethernet MAC, adds motor control timers (MTU3+POE3), no hardware crypto | Optimized for servo drives and inverters - replaces Ethernet with enhanced PWM dead-time control and encoder interfaces | Choose for motion control where IEEE 1588 sync is unnecessary but 3-phase complementary PWM with hardware dead-time is essential |
Compared with R5F564MGHGFC#V1, R5F565NEHDFC#V1 reduces connectivity scope (single Ethernet, no battery charging) while lowering cost, whereas R7FA6M2AF3CFP#AA0 trades networking for motor-specific peripherals - neither offers pin compatibility, but both share RXv2 toolchain and ecosystem alignment.
Availability
R5F564MGHGFC#V1 is available at Aetrix Electronics and suitable for industrial gateways, secure edge controllers, automotive diagnostic tools, and medical data loggers requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for R5F564MGHGFC#V1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader headquartered in Tokyo, Japan, specializing in microcontrollers, analog, power, and SoC solutions for industrial, automotive, and enterprise markets.
The RX64M Group, including R5F564MGHGFC#V1, was designed for high-reliability industrial connectivity applications demanding real-time performance, functional safety (IEC 60730), and integrated security - targeting gateway, control, and edge intelligence roles.
FAQ
What is the maximum operating frequency and CPU architecture of the R5F564MGHGFC#V1?
The R5F564MGHGFC#V1 operates at a maximum frequency of 120 MHz using the 32-bit RXv2 CPU core, delivering 240 DMIPS performance. It includes a single-precision IEEE-754 floating-point unit, dual multiply-accumulate units, and a 5-stage pipeline with variable-length instructions. This architecture enables deterministic real-time execution critical for industrial control loops and protocol stack processing in the R5F564MGHGFC#V1.
Does the R5F564MGHGFC#V1 support IEEE 1588 Precision Time Protocol?
Yes, the R5F564MGHGFC#V1 supports IEEE 1588 through its integrated Ethernet controller (ETHERC) paired with the PTP controller (EPTPC). Hardware timestamping is performed at the MAC layer with nanosecond resolution, enabling master/slave clock synchronization with sub-microsecond accuracy - a core capability confirmed in R01DS0173EJ0120 Section 1.1 and essential for time-sensitive industrial networks using the R5F564MGHGFC#V1.
What are the flash and RAM capacities of the R5F564MGHGFC#V1?
The R5F564MGHGFC#V1 integrates 4 MB of on-chip code flash memory (zero wait states at 120 MHz), 64 KB of reprogrammable data flash (rated for 100,000 erase/write cycles), 512 KB of general-purpose SRAM (no wait states), 32 KB of ECC-protected RAM (SEC-DED), and 8 KB of standby RAM backed by VBATT. These memory resources are explicitly specified for the 176-pin RX64M variants in Table 1.1 of the R5F564MGHGFC#V1 datasheet R01DS0173EJ0120.
Which communication interfaces are available on the R5F564MGHGFC#V1?
The R5F564MGHGFC#V1 provides dual IEEE 1588-compliant Ethernet MACs, one USBA module with full-speed USB 2.0 and battery charging support, three CAN modules (ISO 11898-1), four SCIFA interfaces with 16-byte FIFOs, two RIIC interfaces (1 Mbps max), one QSPI, one RSPI, two SSI audio interfaces, and an SD host interface. All are confirmed for the 176-pin package in Tables 1.1 and 1.2 of the R5F564MGHGFC#V1 datasheet R01DS0173EJ0120.
What is the operating temperature range and package type of the R5F564MGHGFC#V1?
The R5F564MGHGFC#V1 is rated for –40°C to +105°C (G-version) and uses the PLQP0176KB-A package: a 176-pin Low-Profile Fine-Pitch Ball Grid Array measuring 24 mm × 24 mm with 0.5-mm ball pitch. This package is explicitly assigned to the "HG" suffix variant in the RX64M Group datasheet R01DS0173EJ0120 Section 1.1 and supports all 127 GPIOs, dual Ethernet, and USBA functionality.
R5F564MGHGFC#V1 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 176-LQFP
- Series:
- RX
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv2
- Core Size:
- 32-Bit
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, SCI, SPI, SSI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 127
- Program Memory Size:
- 2.5MB (2.5M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 64K x 8
- RAM Size:
- 512K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 29x12b; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F564MGHGFC#V1 FAQ
1.How can I place an order for R5F564MGHGFC#V1 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F564MGHGFC#V1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F564MGHGFC#V1 reliable?
The price and inventory of R5F564MGHGFC#V1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F564MGHGFC#V1 is usually 5 days.
3.What payment methods are accepted for R5F564MGHGFC#V1?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F564MGHGFC#V1 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F564MGHGFC#V1?
R5F564MGHGFC#V1 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F564MGHGFC#V1 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F564MGHGFC#V1?
For technical support, including R5F564MGHGFC#V1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F564MGHGFC#V1 requirements.
6.How does Aetrix verify that R5F564MGHGFC#V1 is sourced from the original manufacturer or authorized distributors?
All R5F564MGHGFC#V1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F564MGHGFC#V1 meets industry standards.
7.What is the process for return or replacement of R5F564MGHGFC#V1?
All R5F564MGHGFC#V1 units undergo pre-shipment inspection (PSI). If there is an issue with R5F564MGHGFC#V1, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F564MGHGFC#V1 part is unused and in its original packaging.
Return procedure for R5F564MGHGFC#V1:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R5F564MGHGFC#V1 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

