Renesas R5F564MGHGFP#V1
- Part No.:
- R5F564MGHGFP#V1
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 100-LQFP
- Datasheet:
-
R5F564MGHGFP#V1.pdf
- Description:
- IC MCU 32BIT 2.5MB FLASH 100LQFP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
R5F564MGHGFP#V1 from Renesas is a 32-bit RXv2 microcontroller targeting industrial automation and networked embedded systems. It operates at 120 MHz (240 DMIPS), integrates 4 MB on-chip code flash, 512 KB SRAM, IEEE 1588-compliant dual Ethernet MAC, full-speed USB 2.0 with battery charging, CAN, SD host interface, and hardware AES/SHA encryption - deployed in factory HMIs, PLC edge gateways, and IIoT protocol converters.
For engineers reviewing the R5F564MGHGFP#V1 datasheet, R5F564MGHGFP#V1 pinout, R5F564MGHGFP#V1 application, or R5F564MGHGFP#V1 equivalent, key selection criteria include dual Ethernet timing precision (IEEE 1588 PTP), real-time deterministic I/O (127 GPIO, ELC event linking), low-power operation (0.3 mA/MHz), integrated security (AES-256, SHA-256), and industrial temperature support (–40°C to +105°C).
Technical Context
The R5F564MGHGFP#V1 implements the RXv2 CPU core with single-precision IEEE-754 FPU, 32-bit multiplier (1-cycle), and divider (2-cycle), enabling high-throughput signal processing and control loop execution. Its memory subsystem includes 4 MB zero-wait-state flash, 512 KB SRAM, 32 KB ECC RAM, and 64 KB data flash rated for 100,000 erase/write cycles.
Peripherals are clocked across four domains: ICLK (up to 120 MHz for CPU), PCLKA (120 MHz for ETHERC/USBA/AES), PCLKB (60 MHz for timers/ADC/DAC), and PCLKC/PCLKD (60 MHz for S12AD units). Dual Ethernet controllers use dedicated EDMAC channels (3 total) and EPTPC blocks compliant with IEEE 1588-2008 for sub-microsecond timestamping and synchronization.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit, 120 MHz max, 240 DMIPS, IEEE-754 FPU, 5-stage pipeline |
| Memory | 4 MB code flash (no wait states), 512 KB SRAM, 32 KB ECC RAM, 64 KB data flash (100k cycles) |
| Connectivity | Dual IEEE 1588 Ethernet MAC, full-speed USB 2.0 with battery charging, 3× CAN, 9× SCI, 4× SCIFA, 2× RIIC, QSPI, SDHI |
| Analog | Two 12-bit ADCs (8+21 ch), 2× 12-bit DACs, on-chip temperature sensor (±1°C), self-diagnostic A/D |
| Timers & I/O | 29 timers including MTU3a (9 ch), TPUa (6 ch), GPTA (4 ch), CMT/CMTW; 127 GPIO with 5-V tolerance, ELC event linking |
| Security & Power | AES-128/192/256, DES/TDES, SHA-1/224/256, 2.7–3.6 V supply, 0.3 mA/MHz typical, –40°C to +105°C (G-version) |
Pinout & Package
Package: PLQP0176KB-A (176-pin LFBGA, 24 × 24 mm, 0.5-mm pitch). Pinout validated per Renesas R01DS0173EJ0120 Rev.1.20, pages 43–102 (pin function mapping for R5F564Mx series).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Power supply inputs | Core (VCC), analog unit 0 (AVCC0), analog unit 1 (AVCC1); all require 2.7–3.6 V with local decoupling |
| XTAL / EXTAL | Main crystal oscillator terminals | Supports 8–24 MHz external crystal for precise system clock generation and IEEE 1588 timebase stability |
| ETH_MDC / ETH_MDIO | Ethernet management interface | IEEE 802.3 MII/RMII management interface for PHY configuration and status polling |
| ETH_TXD0–3 / ETH_RXD0–3 | Ethernet data lanes | Dual 4-lane RMII/MII interface supporting simultaneous 10/100 Mbps full-duplex operation on both ports |
| USB_VBUS / USB_DP / USB_DM | USB 2.0 physical interface | Full-speed USB 2.0 transceiver with integrated battery charging detection (BC1.2 compliant) |
| SD_CLK / SD_CMD / SD_DAT0–3 | SD host interface signals | 4-bit SD bus supporting SD Memory Card v3.01 and SDIO v3.00 at up to 15 MB/s (high-speed mode) |
Key Features
| Feature | Design Value |
|---|---|
| IEEE 1588 Precision Time Protocol Engine | Dedicated EPTPC block synchronized to dual Ethernet MACs enables sub-100 ns timestamp resolution for industrial time-sensitive networking |
| Event Link Controller (ELC) | 119 internal event sources routed without CPU intervention - e.g., timer overflow triggers ADC conversion or GPIO toggle, reducing latency and ISR overhead |
| Hardware Cryptographic Accelerator | On-die AES-256/SHA-256 engine offloads TLS 1.2/1.3 handshake and firmware signature verification, eliminating software crypto bottlenecks |
| Industrial Temperature Grade (G) | Rated for –40°C to +105°C ambient operation with guaranteed performance across full voltage (2.7–3.6 V) and frequency (120 MHz) range |
| Background Operation Support | Code/data flash BGO allows concurrent program/erase while executing from other memory regions - critical for field firmware updates without system halt |
Applications
| Industrial Ethernet Gateway | Smart Energy Metering Hub |
|---|---|
|
Use Scenario: Aggregates Modbus TCP, CANopen, and BACnet/IP traffic across heterogeneous field buses and forwards to cloud via dual Ethernet with QoS tagging. IC Role / Device Role / Timing Role: Primary protocol translation MCU with IEEE 1588 PTP master clock, dual Ethernet MACs, and hardware crypto for secure tunneling. Use Value: Sub-microsecond time synchronization enables deterministic packet scheduling and precise timestamping of energy consumption events. |
Use Scenario: Reads metrology ICs (e.g., ADE7953), logs tamper events, signs usage data cryptographically, and uploads via LTE/Ethernet. IC Role / Device Role / Timing Role: Secure data acquisition controller with 12-bit dual ADC, hardware AES/SHA, RTC with battery backup, and SDHI for local storage. Use Value: On-chip ECC RAM and 100k-cycle data flash ensure 10+ year reliability for meter firmware and tariff tables under frequent write cycles. |
| Factory HMI Controller | IIoT Edge Node |
|
Use Scenario: Drives 7-inch resistive/capacitive touch display via RGB interface, runs lightweight RTOS, handles button/encoder inputs, and communicates over CAN/USB. IC Role / Device Role / Timing Role: Human-machine interface processor with 127 GPIO, USB 2.0 host for peripheral attachment, and real-time timer subsystem (MTU3/TPU/GPT). Use Value: ELC-linked GPIO and timers enable jitter-free encoder position capture and PWM backlight control without CPU polling. |
Use Scenario: Collects vibration, temperature, and current data from sensors, performs FFT-based anomaly detection, and transmits alerts via MQTT over Ethernet/USB. IC Role / Device Role / Timing Role: Sensor fusion node with FPU-accelerated math, 12-bit ADC with self-diagnostic, temperature sensor, and dual Ethernet for redundant uplinks. Use Value: 240 DMIPS + FPU enables real-time spectral analysis on 1024-point FFT within 10 ms - no external DSP required. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F565NEHDFP#V0 | Same RX65N group, 120 MHz, but adds TrustZone-based secure boot and 2 MB flash; lacks dual Ethernet and USB battery charging | Better suited for secure boot-critical applications (e.g., medical devices), not IEEE 1588 time-critical gateways | Select when hardware root-of-trust and secure firmware update are mandatory over dual Ethernet functionality |
| STM32H743ZIT6 | ARM Cortex-M7, 480 MHz, 2 MB flash, 1 MB RAM; single Ethernet MAC, no IEEE 1588 hardware, no integrated USB BC1.2 | Higher raw compute throughput but requires external PHY and software PTP stack for time sync | Prefer when maximum integer/FPU performance is prioritized over deterministic industrial time sync and integrated USB charging |
Compared with R5F564MGHGFP#V1, the R5F565NEHDFP#V0 trades dual Ethernet and USB battery charging for enhanced security features, while the STM32H743ZIT6 delivers higher clock speed but lacks hardware-accelerated IEEE 1588 and integrated USB charging - making R5F564MGHGFP#V1 optimal for time-deterministic industrial gateways requiring minimal external components.
Availability
R5F564MGHGFP#V1 is available at Aetrix Electronics and suitable for industrial automation, smart energy infrastructure, and IIoT edge nodes requiring stable component supply, long-term lifecycle assurance, and automotive-grade reliability under extended temperature operation.
Supply support for R5F564MGHGFP#V1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a Japanese semiconductor manufacturer specializing in microcontrollers, analog, power, and SoC solutions for industrial, automotive, and enterprise markets.
The RX64M Group, including R5F564MGHGFP#V1, was designed for high-performance industrial connectivity - integrating dual IEEE 1588 Ethernet, secure communication, and real-time control in a single chip for factory automation and smart infrastructure.
FAQ
What is the operating temperature range for R5F564MGHGFP#V1?
The R5F564MGHGFP#V1 is a G-version device rated for –40°C to +105°C ambient operation. This industrial temperature grade ensures reliable 120 MHz CPU performance, dual Ethernet timing accuracy, and flash/SRAM retention across harsh factory and outdoor deployment environments - verified per Renesas R01DS0173EJ0120 specification limits.
Does R5F564MGHGFP#V1 support IEEE 1588 hardware timestamping?
Yes, R5F564MGHGFP#V1 includes a dedicated EPTPC (Precision Time Protocol Controller) block tightly coupled to both Ethernet MACs. It provides hardware timestamping with sub-100 ns resolution, PTP slave/master operation, and synchronization to external clocks - enabling deterministic time-sensitive networking without CPU overhead or software stack latency.
How many Ethernet interfaces does R5F564MGHGFP#V1 integrate?
R5F564MGHGFP#V1 integrates two independent IEEE 802.3-compliant Ethernet MACs, each supporting 10/100 Mbps full/half-duplex operation via MII or RMII. Both interfaces feature dedicated EDMAC channels and share access to the EPTPC for synchronized IEEE 1588 operation - confirmed in R01DS0173EJ0120 Section 1.1 and Table 1.2.
What USB capabilities does R5F564MGHGFP#V1 provide?
R5F564MGHGFP#V1 includes one full-speed USB 2.0 module (USBA) with integrated transceiver and battery charging detection (BC1.2 compliant). It supports host/function/OTG modes, 12 Mbps transfer, 8.5 KB on-chip RAM buffer, and requires no external pull-up/pull-down resistors - specifically enabled in 176-pin packages like R5F564MGHGFP#V1 per datasheet Section 1.1.
Is hardware cryptographic acceleration available on R5F564MGHGFP#V1?
Yes, R5F564MGHGFP#V1 includes a dedicated hardware accelerator supporting AES-128/192/256, DES/TDES, and SHA-1/224/256. This engine operates independently of the CPU, enabling high-throughput TLS handshake processing, firmware image signing, and secure boot verification - documented in R01DS0173EJ0120 Section 1.1 "Encryption (optional)".
R5F564MGHGFP#V1 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 100-LQFP
- Series:
- RX
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv2
- Core Size:
- 32-Bit
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, SCI, SPI, SSI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 78
- Program Memory Size:
- 2.5MB (2.5M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 64K x 8
- RAM Size:
- 512K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 29x12b; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F564MGHGFP#V1 FAQ
1.How can I place an order for R5F564MGHGFP#V1 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F564MGHGFP#V1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F564MGHGFP#V1 reliable?
The price and inventory of R5F564MGHGFP#V1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F564MGHGFP#V1 is usually 5 days.
3.What payment methods are accepted for R5F564MGHGFP#V1?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F564MGHGFP#V1 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F564MGHGFP#V1?
R5F564MGHGFP#V1 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F564MGHGFP#V1 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F564MGHGFP#V1?
For technical support, including R5F564MGHGFP#V1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F564MGHGFP#V1 requirements.
6.How does Aetrix verify that R5F564MGHGFP#V1 is sourced from the original manufacturer or authorized distributors?
All R5F564MGHGFP#V1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F564MGHGFP#V1 meets industry standards.
7.What is the process for return or replacement of R5F564MGHGFP#V1?
All R5F564MGHGFP#V1 units undergo pre-shipment inspection (PSI). If there is an issue with R5F564MGHGFP#V1, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F564MGHGFP#V1 part is unused and in its original packaging.
Return procedure for R5F564MGHGFP#V1:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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