Renesas R5F564MJCDFP#V1
- Part No.:
- R5F564MJCDFP#V1
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 100-LQFP
- Datasheet:
-
R5F564MJCDFP#V1.pdf
- Description:
- IC MCU 32BIT 3MB FLASH 100LFQFP
- Quantity:
- Payment:

- Shipping:

Inventory:3,788
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
R5F564MJCDFP#V1 from Renesas is a 120-MHz 32-bit RXv2 microcontroller with integrated FPU, 4 MB code flash, 512 KB SRAM, IEEE 1588-compliant dual Ethernet MAC, full-speed USB 2.0 with battery charging, CAN, SD host interface, and hardware encryption - deployed in industrial gateways requiring deterministic real-time control, secure connectivity, and multi-protocol edge processing.
For engineers reviewing the R5F564MJCDFP#V1 datasheet, R5F564MJCDFP#V1 pinout, R5F564MJCDFP#V1 application, or R5F564MJCDFP#V1 equivalent, key selection considerations include its 176-pin LFBGA (PLQP0176KB-A) package, dual Ethernet + USB + CAN coexistence, 120-MHz deterministic timing, on-chip ECC RAM, and IEC60730 safety support for certified embedded systems.
Technical Context
The R5F564MJCDFP#V1 implements the RXv2 CISC Harvard architecture with 5-stage pipeline, single-cycle 32×32 multiplier, and IEEE-754-compliant FPU delivering 240 DMIPS at 120 MHz. Its clock system supports independent domain scaling: ICLK up to 120 MHz for CPU/core logic, PCLKA up to 120 MHz for Ethernet/USB/AES, and PCLKB up to 60 MHz for timers/ADC/DAC.
It integrates dual ETHERC modules with EPTPC (IEEE 1588 PTP), EDMAC (3-channel DMA), and USBA with 8.5 KB buffer and battery charging detection - all confirmed for the 176-pin variant. The device supports simultaneous operation of two Ethernet ports, one full-speed USB 2.0 port with OTG and BC1.2 compliance, and three CAN channels with 32 mailboxes each.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit, 120 MHz max, 240 DMIPS, IEEE-754 FPU, 5-stage pipeline |
| Memory | 4 MB code flash (no wait states), 64 KB data flash (100k erase cycles), 512 KB SRAM (no wait), 32 KB ECC RAM (SEC-DED) |
| Connectivity | Dual IEEE 1588 Ethernet MAC, full-speed USB 2.0 with battery charging, 3× CAN (ISO 11898-1), 4× SCIFA, 2× RIIC, QSPI, SDHI |
| Analog Peripherals | Two 12-bit S12ADC units (8 + 21 ch), 2× R12DA, on-chip temperature sensor (±1°C), RTC with battery backup |
| Timers & Control | TPUa (6 ch), MTU3a (9 ch), GPTA (4 ch), CMT/CMTW, IWDTa with window function, ELC for event-driven peripheral coordination |
| Package & Environment | PLQP0176KB-A: 176-pin LFBGA, 24 × 24 mm, 0.5-mm pitch, –40°C to +85°C (D-version) |
Pinout & Package
Package: PLQP0176KB-A - 176-pin Low-Profile Fine-Pitch Ball Grid Array (LFBGA), 24 mm × 24 mm, 0.5 mm pitch, RoHS-compliant, lead-free, moisture sensitivity level (MSL) 3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Power supply inputs | Core/analog power domains (2.7–3.6 V); separate AVCC pins enable noise-isolated ADC/DAC operation |
| VBATT | Battery backup supply | Provides continuous power to RTC during main supply loss; enables calendar/timekeeping in deep standby |
| ETXD0–ETXD3 / ETXCK / ETXEN / ERXD0–ERXD3 / ERXDV / ERXER | Ethernet PHY interface (MII) | Supports dual 10/100 Mbps Ethernet with MII/RMII; dedicated pins per channel enable concurrent traffic routing |
| USBDP / USBDM | USB 2.0 differential data pair | Full-speed (12 Mbps) USB transceiver with integrated termination; supports host/function/OTG without external resistors |
| CANH / CANL (CH0–CH2) | CAN bus differential pairs | Three independent ISO 11898-1 compliant CAN interfaces; each with 32 configurable mailboxes and loopback test mode |
| SDCLK / SDCMD / SDDATA0–3 | SD host interface signals | 4-bit SD bus supporting SD memory/SDIO cards up to 15 MB/s; includes CRC7/CRC16 error checking and card-detect interrupt |
Key Features
| Feature | Design Value |
|---|---|
| IEEE 1588 Precision Time Protocol (PTP) | Hardware-accelerated timestamping in EPTPC block enables sub-microsecond time synchronization across industrial Ethernet networks |
| IEC60730 Class B Safety Support | Integrated oscillation-stop detection, CRC calculator, self-diagnostic A/D, register write protection, and IWDTa windowed watchdog for certified functional safety |
| Background Operation (BGO) | Simultaneous code/data flash programming/erasing while executing application code - eliminates runtime interruption for firmware updates |
| Event Link Controller (ELC) | 119 internal event signals routed without CPU intervention - e.g., TPU capture triggers ADC conversion or MTU PWM toggles GPIO |
| Hardware Encryption Acceleration | AES-128/192/256, DES/TDES, SHA-1/224/256, HMAC - offloads crypto operations from CPU, enabling TLS stack execution with <5% overhead |
Applications
| Industrial Ethernet Gateway | Secure Edge PLC Controller |
|---|---|
Use Scenario: Aggregating Modbus TCP, PROFINET, and EtherNet/IP traffic between legacy fieldbus devices and cloud SCADA platforms. IC Role / Device Role / Timing Role: Dual Ethernet MAC + PTP controller synchronizes distributed I/O nodes; USBA enables local HMI USB update; CAN handles legacy motor drives. Use Value: Deterministic 120-MHz RXv2 core executes protocol stacks with <10 µs jitter; hardware crypto secures OTA firmware delivery. | Use Scenario: Running certified ladder logic and motion control algorithms in compact DIN-rail PLCs with secure remote diagnostics. IC Role / Device Role / Timing Role: Real-time scheduler leverages MTU3/GPTA timers for µs-precise PWM generation; ECC RAM ensures data integrity during voltage dips. Use Value: IEC60730-compliant self-tests (CRC, oscillator monitor, A/D diagnostic) satisfy SIL2 certification requirements without external safety MCU. |
| Smart Energy Meter Hub | Automated Test Equipment (ATE) Controller |
Use Scenario: Multi-utility meter aggregation unit collecting AMI data via RF mesh, PLC, and cellular backhaul with tamper-proof logging. IC Role / Device Role / Timing Role: SDHI stores encrypted consumption logs; RTC with VBATT backup maintains time during grid outages; AES engine signs data payloads. Use Value: 64 KB data flash endurance (100k cycles) enables decade-long secure log retention; low-power modes reduce standby current to 0.3 mA/MHz. | Use Scenario: High-speed parametric test controller coordinating PXI instruments, DUT power sequencing, and pass/fail result reporting over Ethernet. IC Role / Device Role / Timing Role: TPUa/MTU3 generate precise stimulus waveforms; parallel data capture (PDC) acquires analog test responses; SCIg interfaces with legacy GPIB adapters. Use Value: 127 GPIOs with 5-V tolerance simplify adapter board design; 12-bit ADC with disconnection detection validates sensor presence pre-test. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-performance industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F565NEDFP#V1 | Same RX65N Group; 2 MB flash, 1.5 MB SRAM, no Ethernet MAC, adds TrustZone-based secure boot | Better suited for security-first applications (e.g., secure bootloader, encrypted key storage) but lacks dual Ethernet required for gateway use | Select when cryptographic isolation outweighs connectivity density; not drop-in due to missing ETHERC/USBA peripherals |
| R7FA6M2AF3CFP#AA0 | RX72M Group; 200 MHz, 1 MB flash, single Ethernet + USB, enhanced graphics acceleration, no SDHI or QSPI | Optimized for HMI-rich edge devices (e.g., panel PCs) rather than protocol-bridging gateways | Choose for higher CPU throughput and display support; incompatible pinout and reduced peripheral set vs. R5F564MJCDFP#V1 |
Compared with R5F565NEDFP#V1 and R7FA6M2AF3CFP#AA0, the R5F564MJCDFP#V1 uniquely balances dual Ethernet, USB battery charging, SDHI, and CAN in a single 176-pin package - making it the only RX-series option for space-constrained industrial gateways requiring concurrent wired/wireless protocol translation without external bridge ICs.
Availability
R5F564MJCDFP#V1 is available at Aetrix Electronics and suitable for industrial gateways, edge PLCs, smart energy hubs, and automated test equipment requiring stable component supply, long-term lifecycle assurance, and traceable sourcing for production programs.
Supply support for R5F564MJCDFP#V1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.
The RX64M Group - including the R5F564MJCDFP#V1 - was designed specifically for industrial automation edge devices demanding real-time determinism, multi-protocol connectivity, functional safety, and hardware-accelerated security in a single-chip solution.
FAQ
What is the maximum operating frequency and core architecture of the R5F564MJCDFP#V1?
The R5F564MJCDFP#V1 operates at a maximum frequency of 120 MHz using the RXv2 32-bit CISC Harvard architecture with 5-stage pipeline. It delivers 240 DMIPS and includes a single-precision IEEE-754 floating-point unit, 32×32-bit multiplier (one-cycle), and 32/32-bit divider (two-cycle). This architecture enables deterministic real-time execution critical for industrial control loops and protocol stacks.
Does the R5F564MJCDFP#V1 support IEEE 1588 Precision Time Protocol, and how is it implemented?
Yes, the R5F564MJCDFP#V1 supports IEEE 1588 PTP via its dedicated EPTPC (Precision Time Protocol Controller) block, tightly coupled to the dual Ethernet MAC (ETHERC). Hardware timestamping occurs at packet ingress/egress with sub-microsecond resolution, and the PTP engine handles sync, delay_req, and follow_up message handling without CPU intervention - essential for time-sensitive networking in industrial automation.
What package type and pin count does the R5F564MJCDFP#V1 use, and is it RoHS-compliant?
The R5F564MJCDFP#V1 uses the PLQP0176KB-A package: a 176-pin Low-Profile Fine-Pitch Ball Grid Array measuring 24 mm × 24 mm with 0.5-mm pitch. It is RoHS-compliant, lead-free, and rated MSL-3. This package supports full peripheral access including dual Ethernet MII, USB, CAN, SDHI, and 127 general-purpose I/O pins with 5-V tolerance on 19 pins.
How many Ethernet and USB interfaces does the R5F564MJCDFP#V1 integrate, and what are their key capabilities?
The R5F564MJCDFP#V1 integrates two IEEE 802.3-compliant Ethernet MACs (10/100 Mbps, MII/RMII) with IEEE 1588 PTP support, and one full-speed USB 2.0 interface (USBA) with battery charging detection (BC1.2), OTG capability, and 8.5 KB on-chip buffer. Unlike the base USBb module, USBA is exclusive to 176/177-pin RX64M variants and requires no external pull-up resistors.
What safety and security features are built into the R5F564MJCDFP#V1 for industrial applications?
The R5F564MJCDFP#V1 includes IEC60730 Class B compliance features: oscillation-stop detection, hardware CRC calculator, self-diagnostic A/D converter, register write protection, and windowed independent watchdog timer (IWDTa). For security, it offers AES-128/192/256, DES/TDES, and SHA-1/224/256 accelerators - enabling TLS 1.2+ and secure boot without external crypto co-processors.
R5F564MJCDFP#V1 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 100-LQFP
- Series:
- RX600
- Packaging:
- Tray
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Core Processor:
- RXv2
- Core Size:
- 32-Bit Single-Core
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, SCI, SPI, SSI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 78
- Program Memory Size:
- 3MB (3M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 64K x 8
- RAM Size:
- 552K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 22x12b; D/A 1x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F564MJCDFP#V1 FAQ
1.How can I place an order for R5F564MJCDFP#V1 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F564MJCDFP#V1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F564MJCDFP#V1 reliable?
The price and inventory of R5F564MJCDFP#V1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F564MJCDFP#V1 is usually 5 days.
3.What payment methods are accepted for R5F564MJCDFP#V1?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F564MJCDFP#V1 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F564MJCDFP#V1?
R5F564MJCDFP#V1 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F564MJCDFP#V1 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F564MJCDFP#V1?
For technical support, including R5F564MJCDFP#V1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F564MJCDFP#V1 requirements.
6.How does Aetrix verify that R5F564MJCDFP#V1 is sourced from the original manufacturer or authorized distributors?
All R5F564MJCDFP#V1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F564MJCDFP#V1 meets industry standards.
7.What is the process for return or replacement of R5F564MJCDFP#V1?
All R5F564MJCDFP#V1 units undergo pre-shipment inspection (PSI). If there is an issue with R5F564MJCDFP#V1, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F564MJCDFP#V1 part is unused and in its original packaging.
Return procedure for R5F564MJCDFP#V1:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R5F564MJCDFP#V1 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

