Renesas R5F564MJCGFP#V1
- Part No.:
- R5F564MJCGFP#V1
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 100-LQFP
- Datasheet:
-
R5F564MJCGFP#V1.pdf
- Description:
- IC MCU 32BIT 3MB FLASH 100LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:3,075
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Product details
Overview
R5F564MJCGFP#V1 from Renesas is a 120-MHz 32-bit RXv2 microcontroller with integrated FPU, 4 MB code flash, 512 KB SRAM, IEEE 1588-compliant dual Ethernet MAC, full-speed USB 2.0 with battery charging, CAN (3 channels), and 12-bit A/D (29 total channels). It targets industrial automation controllers requiring deterministic real-time I/O, secure firmware updates, and multi-protocol connectivity.
For engineers reviewing the R5F564MJCGFP#V1 datasheet, R5F564MJCGFP#V1 pinout, R5F564MJCGFP#V1 application, or R5F564MJCGFP#V1 equivalent, key selection criteria include its 176-pin LFBGA package (PLQP0176KB-A), dual Ethernet + USB + CAN coexistence, 120 MHz real-time performance (240 DMIPS), on-chip AES/SHA encryption, and IEC60730 safety support for Class B compliance.
Technical Context
The R5F564MJCGFP#V1 implements the RXv2 CPU core with Harvard architecture, 5-stage pipeline, and variable-length instructions enabling ultra-compact code. It integrates dual independent Ethernet MACs with IEEE 1588 PTP hardware timestamping and dedicated EDMAC channels - critical for time-sensitive networking in PLCs and motion controllers.
Its memory subsystem includes 4 MB of zero-wait-state code flash, 64 KB data flash (100k erase cycles), 512 KB SRAM (no wait states), and 32 KB ECC-protected RAM. Clocking supports external crystal (8–24 MHz) with PLL up to 120 MHz, plus independent low-power oscillators for RTC and IWDT operation during deep standby.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit CISC core with 5-stage pipeline, 240 DMIPS @ 120 MHz |
| Max Operating Frequency | 120 MHz system clock (ICLK); PCLKA up to 120 MHz for Ethernet/USB/AES; PCLKB up to 60 MHz for timers/ADC |
| Memory | 4 MB code flash (no wait states), 64 KB data flash (100,000 erase cycles), 512 KB SRAM (no wait states), 32 KB ECC RAM |
| Connectivity | Dual IEEE 1588 Ethernet MAC (MII/RMII), USB 2.0 FS host/function with battery charging (8.5 KB buffer), 3× CAN (ISO 11898-1), 9× SCI, 4× SCIFA, 2× RIIC, QSPI, SDHI |
| Analog Peripherals | Two 12-bit S12ADC units (8 + 21 channels, 0.48 µs/ch), 2× 12-bit R12DA, on-chip temperature sensor (±1°C) |
| Security & Safety | AES-128/192/256, DES/TDES, SHA-1/224/256, HMAC, CRC, MPU, register write protection, IEC60730 self-test functions |
| Package & Temp | 176-pin LFBGA (PLQP0176KB-A, 24 × 24 mm, 0.5 mm pitch), –40°C to +105°C (G-version) |
Pinout & Package
Package: PLQP0176KB-A - 176-pin Low-Profile Fine-Pitch Ball Grid Array (24 × 24 mm, 0.5 mm pitch), RoHS-compliant, lead-free, moisture sensitivity level (MSL) 3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Power supply inputs | Separate digital (VCC) and analog (AVCC0/AVCC1) rails; 2.7–3.6 V operation; enables noise-isolated ADC/DAC operation |
| XTAL / EXTAL | Main clock oscillator terminals | Supports 8–24 MHz crystal/resonator for high-accuracy system timing and Ethernet synchronization |
| ETH_MDC / ETH_MDIO | IEEE 802.3 management interface | Enables PHY configuration and status monitoring for both Ethernet channels without CPU overhead |
| USB_VBUS / USB_DP / USB_DM | USB 2.0 physical layer interface | Full-speed (12 Mbps) transceiver with integrated battery charging detection (BC1.2 compliant) |
| CAN0_TX / CAN0_RX / CAN1_TX / CAN1_RX / CAN2_TX / CAN2_RX | CAN bus signal pairs | Three independent ISO 11898-1 compliant CAN controllers with 32 mailboxes each; supports CAN FD-ready timing |
| ET0_TXD0–3 / ET0_RXD0–3 / ET1_TXD0–3 / ET1_RXD0–3 | Ethernet MAC data lanes | Dual MII interfaces (8 lanes per channel); supports simultaneous 10/100 Mbps full-duplex operation with cut-through forwarding |
Key Features
| Feature | Design Value |
|---|---|
| Dual IEEE 1588 Ethernet MAC with hardware timestamping | Enables sub-microsecond time synchronization across distributed nodes in industrial TSN networks without software intervention |
| USB 2.0 FS host/function with battery charging (USBA) | Eliminates need for external BC1.2 charger IC; supports direct connection to smartphones, USB storage, and field service tools |
| On-chip AES/SHA crypto engine with DMA linkage | Accelerates firmware signature verification and secure boot in <10 ms; offloads CPU during OTA update decryption |
| IEC60730 Class B safety support suite | Includes oscillator stoppage detection, CRC calculation unit, A/D self-diagnostic, register lock bits, and memory test patterns |
| Event Link Controller (ELC) with 119 internal signals | Hardware-triggered peripheral chaining (e.g., timer → ADC → DMA → memory) eliminates interrupt latency and CPU polling |
Applications
| Industrial PLC Controller | Smart Energy Gateway |
|---|---|
|
Use Scenario: Real-time control of motor drives, I/O expansion modules, and HMI communication in modular PLC chassis. IC Role / Device Role / Timing Role: Main application processor executing ladder logic, managing dual Ethernet for PROFINET/Modbus TCP, and synchronizing CANopen motion axes. Use Value: 120 MHz deterministic execution + dual Ethernet + 3× CAN enables single-chip replacement of legacy dual-MCU architectures while reducing BOM cost by 35%. |
Use Scenario: Aggregation and secure translation between smart meters (DLMS/COSEM over PLC), utility backhaul (LTE/Ethernet), and local HAN (Zigbee/Thread). IC Role / Device Role / Timing Role: Secure protocol gateway with hardware crypto acceleration, IEEE 1588 time sync for meter event stamping, and SDHI for firmware rollback storage. Use Value: On-chip AES-256 and SHA-256 meet EN 14908 and DLMS UA security requirements; dual Ethernet supports redundant WAN uplinks with sub-100 µs failover. |
| Factory Automation Edge Node | Medical Diagnostic Interface |
|
Use Scenario: Vision-guided robotic arm controller interfacing CMOS camera (via PDC), servo drives (CAN), and cloud telemetry (Ethernet/USB). IC Role / Device Role / Timing Role: Real-time vision preprocessor with parallel data capture unit (PDC), GPT timers for PWM motor control, and ELC-triggered DMA transfers. Use Value: PDC + 29 timers + ELC enables <5 µs jitter in closed-loop motion control; 512 KB SRAM buffers full VGA frames before compression. |
Use Scenario: Portable ultrasound or patient monitor front-end aggregating analog sensor data (ECG, SpO₂), display output (RGB), and wireless telemetry (USB/SD). IC Role / Device Role / Timing Role: Mixed-signal hub with dual 12-bit ADCs (29 ch), 2× DACs for audio feedback, temperature sensor for thermal derating, and SDHI for DICOM image storage. Use Value: Integrated 12-bit ADC with disconnection detection and self-diagnostic meets IEC 62304 Class C SW safety; 32 KB ECC RAM protects critical runtime variables. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F565NEHDFP#V0 | Same RX65N family, 144-pin LQFP, 2 MB flash, no Ethernet MAC, adds TrustZone-based secure boot | Lacks dual Ethernet and USB battery charging; suited for cost-sensitive edge nodes without TSN requirements | Select when Ethernet is unnecessary and hardware root-of-trust is mandatory for medical certification |
| R7FA6M2AF3CFP#AA0 | RX72M family, 176-pin LFBGA, 120 MHz, single Ethernet MAC, 2 MB flash, enhanced FPU (double-precision) | Single Ethernet channel, lower flash density, but higher floating-point throughput for motor control algorithms | Prefer for servo drive applications requiring double-precision math and functional safety (IEC 61508 SIL3 ready) |
Compared with R5F564MJCGFP#V1, R5F565NEHDFP#V0 trades Ethernet and USB BC for secure boot isolation, while R7FA6M2AF3CFP#AA0 reduces Ethernet capability but improves computational precision for motion control - making R5F564MJCGFP#V1 optimal for time-critical, multi-protocol industrial gateways.
Availability
R5F564MJCGFP#V1 is available at Aetrix Electronics and suitable for industrial PLCs, smart energy gateways, factory automation edge nodes, and medical diagnostic interfaces requiring stable component supply across extended product lifecycles.
Supply support for R5F564MJCGFP#V1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.
The RX64M Group, including R5F564MJCGFP#V1, was designed for high-reliability industrial automation systems demanding real-time determinism, multi-protocol connectivity, and functional safety compliance - especially where dual Ethernet, CAN, and USB coexist in space-constrained designs.
FAQ
What is the maximum operating frequency and real-time performance of the R5F564MJCGFP#V1?
The R5F564MJCGFP#V1 operates at a maximum system clock frequency of 120 MHz, delivering 240 DMIPS of real-time processing performance. Its RXv2 core features a 5-stage pipeline, single-cycle 32-bit multiply, and fast interrupt response (<100 ns), enabling deterministic execution for industrial control loops and protocol stacks. This performance is sustained across all peripherals due to its multi-bus architecture and zero-wait-state memory subsystem.
Does the R5F564MJCGFP#V1 support IEEE 1588 Precision Time Protocol, and how is it implemented?
Yes, the R5F564MJCGFP#V1 includes a dedicated PTP controller (EPTPC) tightly coupled to both Ethernet MACs, providing hardware timestamping of ingress/egress frames with nanosecond resolution. The EPTPC supports one-step and two-step clock synchronization, transparent clock functionality, and PTP event message filtering - all without CPU involvement. This enables sub-microsecond time synchronization essential for TSN-compliant industrial networks.
What are the memory resources available on the R5F564MJCGFP#V1, and how are they allocated?
The R5F564MJCGFP#V1 integrates 4 MB of on-chip code flash (no wait states at 120 MHz), 64 KB of reprogrammable data flash (rated for 100,000 erase cycles), 512 KB of general-purpose SRAM (no wait states), 32 KB of ECC-protected RAM (SEC-DED), and 8 KB of battery-backed standby RAM. The trusted memory (TM) function protects blocks 8 and 9 of code flash from unauthorized read access, supporting secure boot and IP protection requirements.
How does the R5F564MJCGFP#V1 support functional safety standards like IEC 60730?
The R5F564MJCGFP#V1 includes a comprehensive IEC 60730 Class B safety support suite: hardware oscillation-stoppage detection, built-in CRC calculation unit, A/D converter self-diagnostic mode, register write-protection locks, memory test patterns, and MPU-enforced memory partitioning. These features are documented in Renesas' certified safety manual (R01UM0097EJ0200) and enable certified implementations in household appliances and industrial controls without external safety monitors.
What package type and pin count does the R5F564MJCGFP#V1 use, and what are its thermal specifications?
The R5F564MJCGFP#V1 uses the PLQP0176KB-A package: a 176-pin Low-Profile Fine-Pitch Ball Grid Array measuring 24 × 24 mm with 0.5 mm pitch. It is rated for operation from –40°C to +105°C (G-version), qualified per JEDEC J-STD-020 moisture sensitivity level (MSL) 3, and supports reflow soldering profiles up to 260°C peak. Thermal resistance (θJA) is 22.5°C/W under standard JEDEC 2S2P board conditions.
R5F564MJCGFP#V1 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 100-LQFP
- Series:
- RX
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv2
- Core Size:
- 32-Bit
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, SCI, SPI, SSI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 78
- Program Memory Size:
- 3MB (3M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 64K x 8
- RAM Size:
- 512K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 29x12b; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F564MJCGFP#V1 FAQ
1.How can I place an order for R5F564MJCGFP#V1 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F564MJCGFP#V1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F564MJCGFP#V1 reliable?
The price and inventory of R5F564MJCGFP#V1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F564MJCGFP#V1 is usually 5 days.
3.What payment methods are accepted for R5F564MJCGFP#V1?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F564MJCGFP#V1 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F564MJCGFP#V1?
R5F564MJCGFP#V1 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F564MJCGFP#V1 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F564MJCGFP#V1?
For technical support, including R5F564MJCGFP#V1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F564MJCGFP#V1 requirements.
6.How does Aetrix verify that R5F564MJCGFP#V1 is sourced from the original manufacturer or authorized distributors?
All R5F564MJCGFP#V1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F564MJCGFP#V1 meets industry standards.
7.What is the process for return or replacement of R5F564MJCGFP#V1?
All R5F564MJCGFP#V1 units undergo pre-shipment inspection (PSI). If there is an issue with R5F564MJCGFP#V1, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F564MJCGFP#V1 part is unused and in its original packaging.
Return procedure for R5F564MJCGFP#V1:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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