Renesas R5F564MJGDFB#31
- Part No.:
- R5F564MJGDFB#31
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 144-LQFP
- Datasheet:
-
R5F564MJGDFB#31.pdf
- Description:
- IC MCU 32BIT 3MB FLASH 144LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:4,785
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Product details
Overview
R5F564MJGDFB#31 from Renesas is a 120-MHz 32-bit RXv2 microcontroller with integrated FPU, 4 MB code flash, 512 KB SRAM, IEEE 1588-compliant dual Ethernet MAC, full-speed USB 2.0 with battery charging, CAN (3 channels), and 12-bit A/D (29 total channels). It targets industrial networking gateways requiring deterministic real-time control, secure connectivity, and high-precision analog sensing.
For engineers reviewing the R5F564MJGDFB#31 datasheet, R5F564MJGDFB#31 pinout, R5F564MJGDFB#31 application, or R5F564MJGDFB#31 equivalent, key selection criteria include its 177-pin TFLGA package, dual Ethernet + USB + CAN coexistence, 120 MHz real-time performance with 240 DMIPS, and IEC60730-ready safety features including CRC, oscillation-stop detection, and self-diagnostic A/D.
Technical Context
The R5F564MJGDFB#31 implements the RXv2 CPU core with CISC Harvard architecture, 5-stage pipeline, and variable-length instructions enabling ultra-compact code. It integrates dual independent Ethernet controllers (ETHERC) with IEEE 1588 PTP support via EPTPC and dedicated EDMAC channels - one for each ETHERC channel plus one for EPTPC - enabling hardware-accelerated time-synchronized packet handling without CPU intervention.
Its clock system combines external crystal (8–24 MHz) with internal PLL and multiple on-chip oscillators (LOCO, HOCO, IWDT-dedicated), allowing independent domain clocks: ICLK up to 120 MHz for CPU, PCLKA up to 120 MHz for Ethernet/USB/AES, PCLKB up to 60 MHz for timers and A/D, and PCLKC/PCLKD at 60 MHz for dual S12AD units - ensuring precise timing isolation across mixed-criticality peripherals.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit CISC Harvard, 120 MHz max, 240 DMIPS - enables deterministic real-time task execution with low cycle count per instruction. |
| Memory | 4 MB code flash (no wait states @120 MHz), 64 KB data flash (100k write cycles), 512 KB SRAM (no wait), 32 KB ECC RAM - supports robust firmware updates and fault-tolerant data storage. |
| Connectivity | Dual IEEE 1588 Ethernet MAC, full-speed USB 2.0 with battery charging, 3× CAN (ISO11898-1), 9× SCI, 4× SCIFA, 2× RIIC, QSPI, SDHI - enables converged industrial edge node with wired redundancy and fieldbus interoperability. |
| Analog Peripherals | Two 12-bit A/D converters (8 + 21 channels), 2× 12-bit D/A, on-chip temperature sensor (±1°C), self-diagnostic A/D - delivers high-fidelity sensor acquisition and closed-loop analog control in compact systems. |
| Security & Safety | AES/DES/SHA crypto acceleration (optional), MPU, register write protection, oscillation-stop detection, CRC unit, IWDT with window function - meets IEC60730 Class B requirements for functional safety certification. |
| Package & Environment | 177-pin TFLGA (8 mm × 8 mm, 0.5 mm pitch), –40°C to +105°C (G-version), 2.7–3.6 V supply - suitable for space-constrained, thermally demanding industrial environments. |
Pinout & Package
Package: TFLGA-177 (PTLG0177KA-A), 8 mm × 8 mm, 0.5 mm pitch, 0.75 mm height, exposed thermal pad.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Power supply inputs | Separate digital (VCC) and analog (AVCC0/AVCC1) rails enable noise isolation for precision A/D and D/A operation. |
| XTAL / EXTAL | Main crystal oscillator terminals | Supports 8–24 MHz external crystal for high-accuracy system clock and IEEE 1588 timebase stability. |
| ETH0_TXD0–3 / ETH0_RXD0–3 / ETH0_RX_ER / ETH0_MDC / ETH0_MDIO | Ethernet PHY interface (Channel 0) | Direct MII connection for 10/100 Mbps Ethernet; supports RMII via pin multiplexing per datasheet configuration. |
| USBA_VBUS / USBA_DP / USBA_DM / USBA_ID | USB 2.0 FS host/function with battery charging | Dedicated USB port with integrated transceiver and 8.5 KB buffer - enables OTG and BC1.2-compliant charging negotiation without external IC. |
| CAN0_TX / CAN0_RX / CAN1_TX / CAN1_RX / CAN2_TX / CAN2_RX | CAN bus transceiver interfaces | Three independent ISO11898-1 compliant CAN channels with 32 mailboxes each - supports multi-bus automotive or industrial diagnostics networks. |
Key Features
| Feature | Design Value |
|---|---|
| IEEE 1588 Precision Time Protocol Engine | Hardware-accelerated timestamping and correction in EPTPC block - eliminates software jitter for sub-microsecond time synchronization in industrial automation. |
| IEC60730 Safety Support | Integrated oscillation-stop detection, CRC calculator, self-test A/D, register lock bits, and IWDT windowing - reduces external safety monitoring components and simplifies Class B certification. |
| Multi-Domain Clock Architecture | Independent ICLK (120 MHz), PCLKA (120 MHz), PCLKB (60 MHz), PCLKC/D (60 MHz) domains - enables concurrent high-speed Ethernet, USB, and A/D sampling without clock contention. |
| Flexible Memory Protection Unit (MPU) | Configurable regions with read/write/execute permissions per privilege level - enforces secure firmware partitioning for bootloader, application, and communication stacks. |
| Event Link Controller (ELC) | 119 internal event sources routed without CPU involvement - allows autonomous timer-triggered A/D conversion, PWM dead-time insertion, or GPIO state changes for deterministic real-time response. |
Applications
| Industrial Ethernet Gateway | Smart Energy Meter Hub |
|---|---|
|
Use Scenario: Aggregating Modbus TCP, CANopen, and BACnet MS/TP traffic into a unified IEEE 1588-synchronized time-stamped Ethernet backbone for substation automation. IC Role / Device Role / Timing Role: Primary real-time controller executing protocol translation, time-aware packet scheduling, and secure TLS offload via AES engine. Use Value: Dual Ethernet + CAN + USB coexistence enables native fieldbus bridging; 120 MHz RXv2 core ensures <100 µs protocol stack latency under 80% CPU load. |
Use Scenario: Multi-tenant energy metering hub collecting pulse outputs, RS485 meter data, and CT/PT analog inputs while providing remote firmware updates over cellular USB tethering. IC Role / Device Role / Timing Role: Central data concentrator with simultaneous A/D sampling (29 ch), secure OTA update via USB battery charging port, and tamper-resistant crypto signing. Use Value: On-chip 12-bit A/D with self-diagnostic and 64 KB data flash enables certified metrology logging; USB BC1.2 support powers cellular modem without auxiliary supply. |
| Programmable Logic Controller (PLC) CPU Module | Factory Automation Edge Node |
|
Use Scenario: Compact PLC mainboard executing IEC 61131-3 logic with motion control loops, EtherCAT slave emulation, and safety monitoring via dual CAN buses. IC Role / Device Role / Timing Role: Deterministic real-time processor running RTOS with hardware-assisted PWM generation (MTU3/GPT), encoder input capture (TPU), and watchdog supervision. Use Value: 29 extended-function timers (including complementary PWM with auto-deadtime) and 127 GPIO pins enable direct I/O expansion without glue logic. |
Use Scenario: Vision-enabled predictive maintenance node capturing CMOS camera frames via PDC, analyzing vibration signatures using FPU-based FFT, and transmitting alerts via encrypted Ethernet. IC Role / Device Role / Timing Role: Embedded vision accelerator with parallel data capture unit (PDC), single-precision FPU for real-time signal processing, and AES-256 for secure cloud telemetry. Use Value: PDC interface eliminates external image FIFO; 240 DMIPS + FPU achieves >15 fps 640×480 frame analysis at 120 MHz - no external DSP required. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-performance industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F566TEADFP#30 | Same RX64M family, 144-pin LFBGA, 2.5 MB flash, 384 KB SRAM, single Ethernet, no USB battery charging | Suitable for cost-optimized gateways without dual Ethernet or USB charging needs | Select when board space and BOM cost constrain require smaller package and reduced peripheral count. |
| R7FA6M2AF3CFB#AA0 | RX72M family, 200 MHz, 2 MB flash, single Ethernet, no IEEE 1588 PTP, enhanced FPU, Arm TrustZone support | Better for security-critical edge AI inference where TrustZone isolation outweighs dual Ethernet need | Choose when hardware-enforced security partitioning is mandatory and IEEE 1588 timestamping is handled externally. |
Compared with R5F564MJGDFB#31, R5F566TEADFP#30 trades dual Ethernet and USB charging for lower pin count and cost, while R7FA6M2AF3CFB#AA0 shifts focus to Arm-based security and higher CPU throughput at the expense of integrated PTP and peripheral concurrency.
Availability
R5F564MJGDFB#31 is available at Aetrix Electronics and suitable for industrial Ethernet gateways, smart energy meter hubs, programmable logic controller CPU modules, and factory automation edge nodes requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for R5F564MJGDFB#31 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and enterprise applications.
The RX64M Group, including R5F564MJGDFB#31, was designed for high-reliability industrial networking applications demanding real-time determinism, functional safety compliance (IEC60730), and converged connectivity - especially where IEEE 1588 time synchronization, dual Ethernet, and fieldbus integration are critical.
FAQ
What is the maximum operating frequency and DMIPS rating of the R5F564MJGDFB#31?
The R5F564MJGDFB#31 operates at a maximum frequency of 120 MHz and delivers 240 DMIPS of processing performance. This is achieved through its RXv2 CPU core with 5-stage pipeline and optimized instruction set. The R5F564MJGDFB#31 maintains this performance across its full operating temperature range (–40°C to +105°C) with no wait states on its 4 MB code flash memory, making it suitable for hard real-time industrial control tasks.
Does the R5F564MJGDFB#31 support IEEE 1588 Precision Time Protocol, and how is it implemented?
Yes, the R5F564MJGDFB#31 includes full hardware support for IEEE 1588-2008 via its integrated EPTPC (PTP Controller for Ethernet) block, which connects directly to both Ethernet MAC channels. It provides hardware timestamping on transmit/receive packets, PTP message parsing, and clock synchronization logic - eliminating software overhead and enabling sub-microsecond time accuracy. The R5F564MJGDFB#31 uses this capability to serve as a boundary clock or transparent clock in industrial time-sensitive networks.
What are the analog capabilities of the R5F564MJGDFB#31, particularly regarding A/D and D/A converters?
The R5F564MJGDFB#31 integrates two independent 12-bit A/D converters: S12AD unit 0 (8 channels) and unit 1 (21 channels), supporting 8/10/12-bit resolution with conversion times as fast as 0.42 µs. It also includes two 12-bit D/A channels with selectable amplifier or direct output. Both A/D units feature self-diagnostic functions, analog input disconnection detection, and hardware-triggered sampling via MTU3/GPT/TPU timers - all essential for certified industrial measurement systems using the R5F564MJGDFB#31.
How does the R5F564MJGDFB#31 support functional safety standards like IEC60730?
The R5F564MJGDFB#31 includes multiple hardware features for IEC60730 Class B compliance: oscillation-stop detection, CRC calculation unit, self-diagnostic A/D converter, register write protection, independent watchdog timer (IWDT) with window function, and memory protection unit (MPU). These allow developers to implement safety mechanisms without external components. The R5F564MJGDFB#31 datasheet documents these features explicitly for Class B qualification, and Renesas provides safety manuals and diagnostic software libraries specifically for this device.
What package type and pin count does the R5F564MJGDFB#31 use, and what are its thermal characteristics?
The R5F564MJGDFB#31 uses a 177-pin TFLGA package (PTLG0177KA-A), measuring 8 mm × 8 mm with 0.5 mm pitch and an exposed thermal pad. It is rated for industrial temperature range (–40°C to +105°C) and operates from a single 2.7–3.6 V supply. Its low-power design draws only 0.3 mA/MHz typical in active mode, and it supports four low-power modes including deep software standby with 8 KB backup RAM - making the R5F564MJGDFB#31 suitable for fanless, sealed industrial enclosures.
R5F564MJGDFB#31 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 144-LQFP
- Series:
- RX600
- Packaging:
- Tray
- Product Status:
- Discontinued at Digi-Key
- Programmable:
- Not Verified
- Core Processor:
- RXv2
- Core Size:
- 32-Bit Single-Core
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, SCI, SPI, SSI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 111
- Program Memory Size:
- 3MB (3M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 64K x 8
- RAM Size:
- 552K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 29x12b; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F564MJGDFB#31 FAQ
1.How can I place an order for R5F564MJGDFB#31 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F564MJGDFB#31 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F564MJGDFB#31 reliable?
The price and inventory of R5F564MJGDFB#31 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F564MJGDFB#31 is usually 5 days.
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Once your R5F564MJGDFB#31 order is processed, you will receive an email with the shipment details and tracking number.
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5.How can I obtain technical support or documentation for R5F564MJGDFB#31?
For technical support, including R5F564MJGDFB#31 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F564MJGDFB#31 requirements.
6.How does Aetrix verify that R5F564MJGDFB#31 is sourced from the original manufacturer or authorized distributors?
All R5F564MJGDFB#31 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F564MJGDFB#31 meets industry standards.
7.What is the process for return or replacement of R5F564MJGDFB#31?
All R5F564MJGDFB#31 units undergo pre-shipment inspection (PSI). If there is an issue with R5F564MJGDFB#31, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F564MJGDFB#31 part is unused and in its original packaging.
Return procedure for R5F564MJGDFB#31:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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