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Renesas R5F564MJGDLK#21
- Part No.:
- R5F564MJGDLK#21
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 145-TFLGA
- Datasheet:
-
R5F564MJGDLK#21.pdf
- Description:
- IC MCU 32BIT 3MB FLASH 145TFLGA
- Quantity:
- Payment:
- Shipping:
Inventory:416
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Product details
Overview
R5F564MJGDLK#21 from Renesas is a 32-bit RXv2 microcontroller operating at up to 120 MHz (240 DMIPS), featuring on-chip 4-MB flash, 512-KB SRAM, IEEE 1588-compliant dual Ethernet MAC, full-speed USB 2.0 with battery charging support, and CAN v2.0B - deployed in industrial gateways requiring deterministic real-time networking, secure firmware updates, and multi-protocol edge connectivity.
For engineers reviewing the R5F564MJGDLK#21 datasheet, R5F564MJGDLK#21 pinout, R5F564MJGDLK#21 application, or R5F564MJGDLK#21 equivalent, key selection criteria include its 177-pin TFLGA package, dual-channel Ethernet with PTP timestamping, hardware AES/SHA encryption, 12-bit dual A/D converters with self-diagnostic capability, and support for IEC 60730 Class B functional safety compliance.
Technical Context
The R5F564MJGDLK#21 implements the RXv2 CPU core with single-precision IEEE-754 FPU, two MAC units, and memory protection unit (MPU), enabling deterministic real-time execution in safety-critical embedded systems. Its clock architecture supports independent domain scaling: ICLK at 120 MHz for CPU/core logic, PCLKA at 120 MHz for Ethernet/USB/AES, and PCLKB at 60 MHz for timers/ADC/DAC.
It integrates dual Ethernet controllers (ETHERC) with dedicated EPTPC hardware compliant with IEEE 1588-2008, supporting hardware timestamping, Pdelay request/response, and sync message handling - essential for time-sensitive networking in industrial automation. The USBA module includes 8.5 KB on-chip RAM and battery charging detection circuitry, exclusive to 176-/177-pin RX64M variants.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit CISC Harvard architecture with 5-stage pipeline, 240 DMIPS @ 120 MHz |
| Flash Memory | 4 MB code flash, zero-wait-state operation at 120 MHz, background programming/erasing supported |
| RAM | 512 KB SRAM (no wait states), 32 KB ECC-protected RAM (SEC-DED), 8 KB standby RAM with VBATT backup |
| Connectivity | Dual IEEE 1588-compliant Ethernet MAC (MII/RMII), full-speed USB 2.0 with battery charging (USBA), 3× CAN v2.0B (32 mailboxes/channel) |
| Analog Peripherals | Two 12-bit A/D converters (8 + 21 channels), 2× 12-bit D/A converters, on-chip temperature sensor (±1°C) |
| Security & Safety | Hardware AES-128/192/256, DES/TDES, SHA-1/224/256, HMAC, IEC 60730 self-test functions including A/D diagnostic and oscillation-stop detection |
| Package | PTLG0177KA-A: 177-pin TFLGA, 8 mm × 8 mm, 0.5-mm pitch, –40°C to +105°C (G-version) |
Pinout & Package
Package: PTLG0177KA-A - 177-pin Thin Fine-Pitch Land Grid Array (TFLGA), 8 mm × 8 mm body, 0.5-mm ball pitch, 0.3-mm ball diameter, lead-free and RoHS-compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC, AVCC0, AVCC1 | Core & analog power supply | Single 2.7–3.6 V supply; AVCC0/AVCC1 independently decoupled for noise-sensitive analog domains |
| VBATT | Battery backup input | Enables RTC operation during main power loss; connects to coin-cell or supercapacitor |
| ETH_MDC / ETH_MDIO | MDIO management interface | Provides PHY register access for dual Ethernet controllers; shared between ETHERC0 and ETHERC1 |
| ETH_TXD0–3 / ETH_RXD0–3 | Ethernet data lanes | Supports MII (4-bit TX/RX) or RMII (2-bit TX/RX + REF_CLK); pin-multiplexed with GPIO |
| USBA_VBUS, USBA_ID, USBA_DP, USBA_DM | USB 2.0 FS transceiver interface | Dedicated USBA pins with integrated PHY; VBUS sensing and battery charging detection enabled |
| CAN0_TX / CAN0_RX / CAN1_TX / CAN1_RX / CAN2_TX / CAN2_RX | CAN physical layer I/O | Three independent CAN channels; each pair supports ISO 11898-1 high-speed differential signaling |
Key Features
| Feature | Design Value |
|---|---|
| IEEE 1588 Hardware Timestamping | Dedicated EPTPC block enables sub-100 ns PTP timestamp accuracy without CPU intervention |
| Secure Boot & Firmware Updates | Trusted Memory (TM) blocks 8–9 prevent read-out of critical bootloader or crypto keys from flash |
| Functional Safety Support | Integrated CRC calculator, IWDTa with window function, A/D self-diagnostic, and register write protection for IEC 60730 Class B |
| Low-Power Real-Time Operation | Four low-power modes including deep software standby with 8 KB RAM retention and RTC wake-up via external event or timer |
| Flexible Clock Domain Control | Independent PLL, HOCO/LOCO sources, and programmable dividers allow per-peripheral clock tuning (e.g., PCLKA = 120 MHz for Ethernet, PCLKB = 60 MHz for ADC) |
Applications
| Industrial Ethernet Gateway | Smart Energy Metering Hub |
|---|---|
|
Use Scenario: Aggregating Modbus TCP, CANopen, and BACnet/IP traffic across factory-floor devices into a unified OPC UA server. IC Role / Device Role / Timing Role: Primary application processor with dual Ethernet MACs handling concurrent PTP-synchronized control loops and time-stamped diagnostics. Use Value: Hardware-accelerated IEEE 1588 timestamping eliminates software jitter, enabling <1 µs inter-device synchronization accuracy for motion control networks. |
Use Scenario: Multi-tariff electricity meter with grid communication (PRIME, G3-PLC), tamper detection, and local HMI via SD card logging. IC Role / Device Role / Timing Role: Secure host MCU managing encrypted firmware updates over PRIME PLC, real-time tariff switching via RTC alarm, and SDHI-based secure log storage. Use Value: On-chip AES-256 and SHA-256 enable end-to-end firmware signature verification and secure boot - meeting IEC 62056-62 and DLMS/COSEM security requirements. |
| Medical Infusion Pump Controller | Automotive Diagnostic Tool (OBD-II) |
|
Use Scenario: Closed-loop infusion delivery system requiring FDA Class II compliance, flow rate precision, and wireless update capability. IC Role / Device Role / Timing Role: Safety-certified controller executing IEC 62304-compliant tasks: motor PWM generation (GPTA), pressure sensor A/D acquisition (S12ADC), and USB-based calibration upload. Use Value: Dual 12-bit A/D converters with self-diagnostic and disconnection detection ensure continuous analog signal integrity monitoring - satisfying IEC 62304 Annex C safety requirements. |
Use Scenario: Handheld OBD-II scanner supporting UDS, KWP2000, and CAN FD diagnostics across legacy and modern vehicles. IC Role / Device Role / Timing Role: Protocol translation engine interfacing with vehicle CAN bus (via three independent CAN modules), USB host for PC connection, and SD card for diagnostic session logging. Use Value: Three CAN channels with 32 mailboxes each allow simultaneous monitoring of powertrain, chassis, and body networks - eliminating polling delays and enabling real-time fault correlation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F565NEGDFP#30 | Same RX64M family, 144-pin LQFP, 2.5 MB flash, no USBA or dual Ethernet; single ETHERC only | Lacks IEEE 1588 PTP hardware and battery-charging USB; suitable for cost-sensitive single-network edge nodes | Select when dual Ethernet and USB battery charging are unnecessary and PCB layout favors LQFP over TFLGA |
| R7FA6M2AF3CFP#AA0 | RX72M family successor: higher 240 MHz CPU, enhanced EtherCAT slave support, but no USBA or SDHI | Targets motion control with EtherCAT; lacks SD host and USB battery charging required for field-service tools | Choose for next-gen designs needing EtherCAT or higher compute; avoid if existing R5F564MJGDLK#21 firmware relies on SDHI or USBA features |
Compared with R5F564MJGDLK#21, R5F565NEGDFP#30 reduces footprint and cost but sacrifices dual PTP Ethernet and USB battery charging, while R7FA6M2AF3CFP#AA0 upgrades CPU performance and EtherCAT capability at the expense of SD host and battery-aware USB - making R5F564MJGDLK#21 uniquely balanced for field-deployable, multi-interface industrial gateways.
Availability
R5F564MJGDLK#21 is available at Aetrix Electronics and suitable for industrial gateways, smart energy meters, medical infusion pumps, and automotive diagnostic tools requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for R5F564MJGDLK#21 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader headquartered in Tokyo, Japan, specializing in microcontrollers, analog, power, and SoC solutions for industrial, automotive, and enterprise applications.
The RX64M Group - including R5F564MJGDLK#21 - was designed for high-reliability industrial networking applications demanding real-time determinism, functional safety certification, and multi-protocol connectivity in compact form factors.
FAQ
What is the maximum operating frequency and CPU architecture of the R5F564MJGDLK#21?
The R5F564MJGDLK#21 operates at a maximum frequency of 120 MHz using the 32-bit RXv2 CPU core, delivering 240 DMIPS performance. It features a 5-stage pipeline, single-precision IEEE-754 floating-point unit, two multiply-accumulate units, and memory protection unit (MPU) - all confirmed in the official R01DS0173EJ0120 datasheet Rev.1.20. This architecture enables deterministic real-time execution in industrial control applications where R5F564MJGDLK#21 serves as the primary system controller.
Does the R5F564MJGDLK#21 support IEEE 1588 Precision Time Protocol hardware acceleration?
Yes, the R5F564MJGDLK#21 integrates a dedicated IEEE 1588-compliant PTP controller (EPTPC) linked to both Ethernet MACs, enabling hardware timestamping of Pdelay_Req, Pdelay_Resp, Sync, and Delay_Req messages with sub-100 ns resolution. This capability is exclusive to 176-/177-pin RX64M variants like R5F564MJGDLK#21 and is documented on page 7 of the R01DS0173EJ0120 datasheet. It eliminates software-induced jitter in time-sensitive networking deployments.
What package type and thermal rating does the R5F564MJGDLK#21 use?
The R5F564MJGDLK#21 uses the PTLG0177KA-A package: a 177-pin Thin Fine-Pitch Land Grid Array measuring 8 mm × 8 mm with 0.5-mm ball pitch. It is rated for the G-version industrial temperature range of –40°C to +105°C, validated per Renesas specification R01DS0173EJ0120. This TFLGA package supports high-density PCB layouts and thermal dissipation requirements typical of fanless industrial gateway enclosures where R5F564MJGDLK#21 is commonly deployed.
Which USB functionality is available on the R5F564MJGDLK#21?
The R5F564MJGDLK#21 includes the USBA module - a full-speed USB 2.0 host/function interface with integrated transceiver and battery charging detection circuitry, accessible only on 176-/177-pin packages. It provides 8.5 KB on-chip RAM for endpoint buffers and supports OTG operation (excluding low-speed mode). This differs from the USBb module found on smaller-pin-count variants and is explicitly confirmed for R5F564MJGDLK#21 in Table 1.2 of the R01DS0173EJ0120 datasheet.
How many CAN interfaces does the R5F564MJGDLK#21 support, and what protocol versions are implemented?
The R5F564MJGDLK#21 supports three independent CAN modules (CAN0, CAN1, CAN2), each compliant with ISO 11898-1 for standard (11-bit) and extended (29-bit) frame formats. Each channel provides 32 configurable mailboxes with programmable acceptance filtering and FIFO buffering. This triple-CAN capability is confirmed in Section 1.1 "Outline of Specifications" (page 7) of the R01DS0173EJ0120 datasheet and enables R5F564MJGDLK#21 to concurrently manage powertrain, chassis, and body networks in automotive diagnostic tools.
R5F564MJGDLK#21 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 145-TFLGA
- Series:
- RX600
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- RXv2
- Core Size:
- 32-Bit Single-Core
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, SCI, SPI, SSI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 111
- Program Memory Size:
- 3MB (3M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 64K x 8
- RAM Size:
- 552K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 29x12b; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F564MJGDLK#21 FAQ
1.How can I place an order for R5F564MJGDLK#21 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F564MJGDLK#21 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F564MJGDLK#21 reliable?
The price and inventory of R5F564MJGDLK#21 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F564MJGDLK#21 is usually 5 days.
3.What payment methods are accepted for R5F564MJGDLK#21?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F564MJGDLK#21 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F564MJGDLK#21?
R5F564MJGDLK#21 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F564MJGDLK#21 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F564MJGDLK#21?
For technical support, including R5F564MJGDLK#21 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F564MJGDLK#21 requirements.
6.How does Aetrix verify that R5F564MJGDLK#21 is sourced from the original manufacturer or authorized distributors?
All R5F564MJGDLK#21 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F564MJGDLK#21 meets industry standards.
7.What is the process for return or replacement of R5F564MJGDLK#21?
All R5F564MJGDLK#21 units undergo pre-shipment inspection (PSI). If there is an issue with R5F564MJGDLK#21, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F564MJGDLK#21 part is unused and in its original packaging.
Return procedure for R5F564MJGDLK#21:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R5F564MJGDLK#21 Tags
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