Renesas R5F564MLCDFB#31
- Part No.:
- R5F564MLCDFB#31
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 144-LQFP
- Datasheet:
-
R5F564MLCDFB#31.pdf
- Description:
- IC MCU 32BIT 4MB FLASH 144LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:2,953
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Product details
Overview
R5F564MLCDFB#31 from Renesas is a 120-MHz 32-bit RXv2 microcontroller with single-precision IEEE-754 FPU, 4 MB on-chip code flash, 512 KB SRAM (no wait states), and integrated IEEE 1588-compliant Ethernet MAC - deployed in industrial gateways requiring deterministic real-time control, secure firmware updates, and dual-protocol connectivity (CAN + Ethernet).
For engineers reviewing the R5F564MLCDFB#31 datasheet, R5F564MLCDFB#31 pinout, R5F564MLCDFB#31 application, or R5F564MLCDFB#31 equivalent, this MCU supports IEC 60730 safety compliance, hardware AES/SHA encryption, dual 12-bit ADCs (29 total channels), full-speed USB 2.0 with battery charging, and SD host interface - critical for BOM-stable design of networked edge controllers.
Technical Context
The R5F564MLCDFB#31 implements the RXv2 CPU core with 240 DMIPS at 120 MHz, Harvard architecture, 5-stage pipeline, and variable-length instructions enabling ultra-compact code density. It integrates dual clock domains: ICLK up to 120 MHz for CPU and high-speed peripherals (ETHERC, USBA, AES), and PCLKB up to 60 MHz for timers, ADCs, and communication interfaces.
Its memory subsystem includes 4 MB code flash (120 MHz, zero-wait), 64 KB data flash (100,000 write cycles), 512 KB SRAM (no wait), 32 KB ECC RAM (SEC-DED), and 8 KB standby RAM. Peripheral integration features two IEEE 1588-capable Ethernet MACs, three CAN modules (32 mailboxes each), nine SCIs, four SCIFAs, two RIICs, QSPI, SDHI, and parallel camera capture (PDC) - all mapped to 127 GPIOs with 5-V tolerance on 19 pins.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit CISC core with 5-stage pipeline, 240 DMIPS @ 120 MHz, IEEE-754 single-precision FPU |
| Flash Memory | 4 MB code flash (120 MHz, zero-wait access); 64 KB data flash (100,000 erase/write cycles) |
| RAM | 512 KB SRAM (no wait), 32 KB ECC RAM (SEC-DED), 8 KB standby RAM (VBATT-backed) |
| Connectivity | 2× IEEE 1588 Ethernet MAC (MII/RMII), 3× CAN (ISO 11898-1), 1× SDHI (15 MB/s), 1× QSPI, 9× SCI/SCIg/SCIh |
| Analog Peripherals | 2× 12-bit S12ADC (8 + 21 channels, 0.48 µs/ch), 2× R12DA (12-bit, amplifier/direct output), on-die temperature sensor (±1°C) |
| Security & Safety | AES-128/192/256, DES/TDES, SHA-1/224/256, HMAC, CRC, IWDTa with window function, MPU, register write protection |
| Package & Temp | LFBGA-176 (13 × 13 mm, 0.8-mm pitch), industrial grade (–40°C to +105°C) |
Pinout & Package
LFBGA-176 package (PLBG0176GA-A), 13 × 13 mm body, 0.8-mm ball pitch, 127 general-purpose I/O pins with 5-V tolerance on 19 pins, open-drain capability, and programmable pull-up resistors.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Core & analog power supply | Single 2.7–3.6 V supply; separate analog domains enable noise-isolated ADC/DAC operation |
| VBATT | Battery backup input | Supplies RTC during main power loss; enables calendar/timekeeping in deep software standby |
| RES# | Active-low reset input | Hardware reset initiation; supports external watchdog or power-monitoring IC assertion |
| EXTAL / XTAL | Main crystal oscillator terminals | Supports 8–24 MHz external crystal; required for IEEE 1588 timestamp accuracy and USB clock derivation |
| MD0 / MD1 | Mode setting pins | Determine boot mode (SCI/USB/user) and single-chip vs. extended mode at power-on reset |
| ETXD0–ETXD3 / ETXCK / ERXD0–ERXD3 / ERXCK | Ethernet PHY interface | MII-mode signals for 10/100 Mbps full/half-duplex; direct connection to external PHY without level-shifting |
Key Features
| Feature | Design Value |
|---|---|
| IEEE 1588 Precision Time Protocol | Hardware-accelerated timestamping in EPTPC block synchronized to Ethernet frames - enables sub-microsecond time synchronization for industrial automation |
| IEC 60730 Class B Support | Integrated oscillation-stop detection, CRC engine, self-diagnostic A/D converter, register write protection, and IWDTa with configurable window - reduces external safety component count |
| Background Operation (BGO) | Simultaneous code/data flash programming/erasing while CPU executes from other memory - enables seamless firmware updates without runtime interruption |
| Event Link Controller (ELC) | 119 internal event signals routed without CPU intervention - e.g., TPU capture triggers ADC conversion, MTU3 PWM edges trigger GPIO toggles |
| Secure Boot & Trusted Memory | TM function blocks read access to flash blocks 8–9; combined with AES decryption, enforces authenticated firmware execution from protected memory regions |
Applications
| Industrial Ethernet Gateway | Smart Energy Metering Hub |
|---|---|
|
Use Scenario: Aggregates Modbus TCP, CANopen, and DLMS/COSEM data from field devices into time-synchronized IEEE 1588 packets for cloud telemetry. IC Role / Device Role / Timing Role: Primary controller with dual Ethernet MACs handling packet routing, timestamping, and protocol translation; RTC maintains UTC-aligned logging. Use Value: Hardware PTP eliminates software timestamp jitter; 4 MB flash stores multiple firmware images for A/B update rollback; ECC RAM ensures data integrity during power brownouts. |
Use Scenario: Manages multi-tariff billing, tamper detection, and HAN (Home Area Network) communication via PLC/RF mesh in DIN-rail mounted meters. IC Role / Device Role / Timing Role: Real-time scheduler coordinating pulse counting (metering), secure crypto (AES-128 for DLMS), and dual-channel ADC sampling of voltage/current waveforms. Use Value: Dual 12-bit ADCs with self-diagnostic and disconnection detection meet IEC 62053 accuracy requirements; 100,000-cycle data flash logs tamper events over 15+ years. |
| Factory Automation PLC I/O Module | Medical Infusion Pump Controller |
|
Use Scenario: Controls distributed I/O expansion via EtherCAT or PROFINET, managing digital inputs, analog outputs, and motion profiles for servo drives. IC Role / Device Role / Timing Role: Deterministic real-time executor using MTU3/GPT PWM with dead-time generation for 3-phase inverter control; ELC links encoder feedback to timer capture. Use Value: Complementary PWM output mode generates non-overlapping gate signals; 127 GPIOs support mixed 24 V DC and 5 V logic interfacing; -40°C to +105°C rating suits cabinet-mounted deployment. |
Use Scenario: Regulates fluid delivery rate, monitors occlusion pressure, validates dose history, and communicates via USB HID to clinical tablets. IC Role / Device Role / Timing Role: Safety-critical controller executing IEC 62304-compliant tasks: motor control (GPTA PWM), pressure sensing (S12ADC), battery charging (USBA), and encrypted audit log storage. Use Value: IWDTa with window function prevents runaway code; 32 KB ECC RAM protects therapy parameters; USB battery charging supports bedside tablet recharging without external adapters. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F565NEDDFB#30 | Same RX65N Group; 2 MB flash, 384 KB SRAM, no Ethernet MAC, adds TrustZone-based secure boot | Targeted at cost-sensitive IoT edge nodes where network security > deterministic timing; lacks IEEE 1588 and dual CAN | Select when cryptographic isolation and lower BOM cost outweigh need for hardware time sync and industrial bus redundancy |
| R7FA6M2AF3CFB#AA0 | RX72M Group; 200 MHz, 1 MB flash, 256 KB SRAM, single Ethernet MAC, enhanced GPTA with 3-phase PWM | Optimized for servo drive control with higher PWM resolution; smaller flash limits complex protocol stacks | Prefer for motion-control-centric designs needing faster PWM update rates, but verify SDHI and QSPI compatibility for legacy firmware reuse |
Compared with R5F564MLCDFB#31, R5F565NEDDFB#30 trades Ethernet and CAN bandwidth for TrustZone security and lower cost, while R7FA6M2AF3CFB#AA0 increases CPU throughput and PWM precision at the expense of flash capacity and dual Ethernet - making R5F564MLCDFB#31 optimal for full-featured industrial gateways requiring both protocol richness and time-critical determinism.
Availability
R5F564MLCDFB#31 is available at Aetrix Electronics and suitable for industrial gateways, smart metering hubs, factory PLC I/O modules, and medical infusion pump controllers requiring stable component supply across multi-year production cycles.
Supply support for R5F564MLCDFB#31 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and enterprise applications.
The RX64M Group, including R5F564MLCDFB#31, was designed for high-integration industrial control systems demanding real-time determinism, functional safety (IEC 60730), and secure connectivity - bridging legacy fieldbuses with modern Ethernet time-sensitive networking.
FAQ
What is the maximum operating frequency and DMIPS performance of the R5F564MLCDFB#31?
The R5F564MLCDFB#31 operates at a maximum frequency of 120 MHz and delivers 240 DMIPS performance. This is achieved through its RXv2 CPU core with 5-stage pipeline, single-cycle 32-bit multiply, and integrated single-precision IEEE-754 floating-point unit - enabling efficient execution of control algorithms and signal processing in real-time industrial applications.
Does the R5F564MLCDFB#31 support IEEE 1588 Precision Time Protocol, and how is it implemented?
Yes, the R5F564MLCDFB#31 supports IEEE 1588 via its dedicated EPTPC (PTP Controller for Ethernet) block, which is hardware-integrated with the dual Ethernet MACs. Timestamping occurs at the physical layer boundary with sub-microsecond accuracy, independent of CPU load - essential for time-sensitive networking in industrial automation and power substations.
How many analog-to-digital converter channels does the R5F564MLCDFB#31 provide, and what are their key capabilities?
The R5F564MLCDFB#31 integrates two independent 12-bit S12ADC units: Unit 0 offers 8 channels with channel-dedicated sample-and-hold, and Unit 1 provides 21 channels. Both support 8/10/12-bit resolution, self-diagnostic voltage generation, analog input disconnection detection, and conversion start triggering by timers or external events - meeting IEC 61000-4-30 Class A measurement requirements.
What security features are included in the R5F564MLCDFB#31 for firmware and data protection?
The R5F564MLCDFB#31 includes AES-128/192/256, DES/TDES, and SHA-1/224/256 cryptographic accelerators; Trusted Memory (TM) to lock flash blocks 8–9; MPU for memory region protection; register write protection; and IWDTa with configurable window function - collectively supporting IEC 62443-3-3 SL2 and IEC 60730 Class B compliance without external security ICs.
What is the package type and thermal specification of the R5F564MLCDFB#31?
The R5F564MLCDFB#31 uses a PLBG0176GA-A LFBGA-176 package (13 × 13 mm, 0.8-mm pitch) rated for industrial temperature range (–40°C to +105°C). Its 127 GPIOs include 19 pins with 5-V tolerance, enabling direct interfacing with legacy 5 V sensors and actuators without level shifters - critical for retrofit industrial equipment.
R5F564MLCDFB#31 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 144-LQFP
- Series:
- RX600
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- RXv2
- Core Size:
- 32-Bit Single-Core
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, SCI, SPI, SSI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 111
- Program Memory Size:
- 4MB (4M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 64K x 8
- RAM Size:
- 552K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 29x12b; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F564MLCDFB#31 FAQ
1.How can I place an order for R5F564MLCDFB#31 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F564MLCDFB#31 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F564MLCDFB#31 reliable?
The price and inventory of R5F564MLCDFB#31 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F564MLCDFB#31 is usually 5 days.
3.What payment methods are accepted for R5F564MLCDFB#31?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F564MLCDFB#31 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F564MLCDFB#31?
R5F564MLCDFB#31 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F564MLCDFB#31 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F564MLCDFB#31?
For technical support, including R5F564MLCDFB#31 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F564MLCDFB#31 requirements.
6.How does Aetrix verify that R5F564MLCDFB#31 is sourced from the original manufacturer or authorized distributors?
All R5F564MLCDFB#31 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F564MLCDFB#31 meets industry standards.
7.What is the process for return or replacement of R5F564MLCDFB#31?
All R5F564MLCDFB#31 units undergo pre-shipment inspection (PSI). If there is an issue with R5F564MLCDFB#31, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F564MLCDFB#31 part is unused and in its original packaging.
Return procedure for R5F564MLCDFB#31:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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