Renesas R5F564MLCDFC#V1
- Part No.:
- R5F564MLCDFC#V1
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 176-LQFP
- Datasheet:
-
R5F564MLCDFC#V1.pdf
- Description:
- IC MCU 32BIT 4MB FLASH 176LFQFP
- Quantity:
- Payment:

- Shipping:

Inventory:1,574
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
R5F564MLCDFC#V1 from Renesas is a 120-MHz 32-bit RXv2 microcontroller with integrated FPU, 4 MB code flash, 512 KB SRAM, IEEE 1588-compliant dual Ethernet MAC, full-speed USB 2.0 with battery charging, CAN (3 channels), and 12-bit A/D (29 total channels). It targets industrial automation controllers requiring real-time deterministic I/O, secure firmware updates, and multi-protocol connectivity.
For engineers reviewing the R5F564MLCDFC#V1 datasheet, R5F564MLCDFC#V1 pinout, R5F564MLCDFC#V1 application, or R5F564MLCDFC#V1 equivalent, key selection considerations include its 176-pin LFBGA package, dual Ethernet + USB + CAN coexistence, 120 MHz real-time performance with 240 DMIPS, and support for IEC 60730 Class B functional safety compliance via hardware CRC, IWDT, and self-diagnostic A/D.
Technical Context
The R5F564MLCDFC#V1 implements the RXv2 CPU core with Harvard architecture, 5-stage pipeline, and variable-length instructions enabling ultra-compact code density. It integrates dual independent Ethernet MACs (ETHERC) with IEEE 1588 PTP timing engine (EPTPC), each backed by dedicated EDMAC channels and 4 KB receive/2 KB transmit FIFOs.
Its clock system supports simultaneous operation at multiple domains: ICLK up to 120 MHz for CPU execution, PCLKA up to 120 MHz for high-speed peripherals (Ethernet, USB, AES), and PCLKB up to 60 MHz for timers and A/D converters - enabling precise peripheral timing isolation without CPU intervention.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit CISC with 5-stage pipeline, 240 DMIPS @ 120 MHz - enables deterministic real-time control loops with sub-µs interrupt latency. |
| Memory | 4 MB code flash (no wait states @ 120 MHz), 512 KB SRAM (no wait), 64 KB data flash (100k write cycles) - supports field-upgradable firmware with background erase. |
| Connectivity | Dual IEEE 1588 Ethernet MAC + full-speed USB 2.0 with battery charging + 3× CAN 2.0B - allows converged industrial networking with time-synchronized motion control and device charging. |
| Analog Peripherals | Two 12-bit A/D units (8 + 21 channels, 0.48 µs conversion), 2× 12-bit D/A, on-chip temperature sensor (±1°C) - enables closed-loop analog sensing and actuation without external signal conditioning. |
| Security & Safety | AES-128/192/256, SHA-1/224/256, HMAC, CRC unit, IWDT with window function, A/D self-diagnostic - meets IEC 60730 Class B requirements for embedded safety-critical firmware. |
| Package & Temp | LFBGA-176 (13 × 13 mm, 0.8 mm pitch), –40°C to +105°C (G-grade) - suitable for convection-cooled industrial enclosures with extended thermal margins. |
Pinout & Package
Package: PLBG0176GA-A (13 × 13 mm, 0.8-mm pitch LFBGA, 176 pins).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Power supply inputs | Separate digital (VCC) and analog (AVCC0/AVCC1) rails enable noise isolation for precision A/D and D/A operation. |
| MTCLKA / MTCLKB / MTCLKC / MTCLKD | Timer clock inputs | Dedicated timer clock sources allow independent frequency scaling for MTU3/GPT channels without affecting system clock domain. |
| ETXD0–7 / ETXCK / ERXD0–7 / ERXCK | Ethernet PHY interface | Full MII interface pins for dual Ethernet channels - supports simultaneous 10/100 Mbps full-duplex operation with hardware timestamping. |
| USBDP / USBDM / USBVBUS | USB 2.0 physical layer | Differential DP/DM pair + VBUS detection enables self-powered or bus-powered USB device/host operation with battery charging negotiation. |
| TXDn / RXDn / RTSn / CTSn | SCI/SCIFA serial interface | Hardware flow control (RTS/CTS) and 16-byte FIFO per channel ensure reliable high-throughput UART communication in noisy industrial environments. |
Key Features
| Feature | Design Value |
|---|---|
| IEEE 1588 PTP Hardware Timestamping | Sub-100 ns timestamp resolution on both Ethernet channels enables precise time synchronization for distributed motion control systems. |
| Event Link Controller (ELC) | 119 internal event signals routed without CPU intervention - e.g., TPU PWM edge triggers A/D conversion, eliminating software jitter in sensor sampling. |
| On-chip Memory Protection Unit (MPU) | Configurable memory regions with read/write/execute permissions - enforces firmware partitioning for secure bootloader and application separation. |
| Background Operation (BGO) | Simultaneous code flash programming/erasing while executing from other flash banks - enables zero-downtime firmware updates in deployed systems. |
| IEC 60730 Self-Diagnostic Suite | Integrated A/D self-test, oscillator stoppage detection, register write protection, and CRC accelerator - reduces external safety monitoring components. |
Applications
| Industrial PLC Controller | Smart Energy Gateway |
|---|---|
Use Scenario: Programmable logic controller managing motor drives, I/O modules, and HMI over EtherCAT or Modbus TCP. IC Role / Device Role / Timing Role: Main application processor executing real-time control tasks, managing dual Ethernet for fieldbus and management networks, and synchronizing motion axes via IEEE 1588. Use Value: 120 MHz deterministic execution + dual Ethernet + hardware PTP eliminates need for external timing ICs and reduces system BOM cost by 18% vs. dual-MCU solutions. |
Use Scenario: Grid-edge energy meter aggregating data from smart meters, inverters, and sensors via CAN, USB, and Ethernet. IC Role / Device Role / Timing Role: Secure data concentrator performing encrypted TLS offload, time-stamped event logging, and firmware validation before OTA updates. Use Value: Integrated AES/SHA accelerators + 4 MB flash + 64 KB data flash enable signed firmware updates with rollback protection and tamper-resistant audit logs. |
| Factory Automation HMI | Medical Diagnostic Interface |
Use Scenario: Touch-based human-machine interface with local graphics rendering and remote diagnostics via USB and Ethernet. IC Role / Device Role / Timing Role: Application host running lightweight GUI stack, managing USB HID/MS class devices, and streaming diagnostic logs over Ethernet with PTP-tagged timestamps. Use Value: On-chip 512 KB SRAM eliminates external SDRAM, reducing EMI and board area; USB battery charging supports portable service tablets. |
Use Scenario: Ultrasound or patient monitor front-end acquiring analog sensor data, processing waveforms, and transmitting DICOM over Ethernet. IC Role / Device Role / Timing Role: Mixed-signal controller interfacing 29-channel A/D, driving DAC outputs for beamforming, and securing HIPAA-compliant data transmission. Use Value: Dual 12-bit A/D units with sample-and-hold and self-diagnostic meet FDA Class II analog accuracy requirements without calibration hardware. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F565NEHDFC#V0 | Same RX65N family, 176-pin LFBGA, but adds 2 MB SRAM and TrustZone security; lacks USB battery charging PHY. | Better suited for secure cloud-connected gateways requiring ARM TrustZone isolation; not drop-in for USB charging use cases. | Select when hardware-enforced secure boot and encrypted RAM are required over USB charging capability. |
| R7FA6M2AF3CFB#AA0 | RX72M series, 176-pin LQFP, 200 MHz CPU, single Ethernet, no USB battery charging; adds CAN FD support. | Higher CPU throughput for complex motion algorithms; CAN FD replaces legacy CAN for automotive diagnostics integration. | Choose for next-gen motion control where CAN FD bandwidth and 200 MHz compute outweigh dual Ethernet needs. |
Compared with R5F564MLCDFC#V1, R5F565NEHDFC#V0 prioritizes security isolation over USB power delivery, while R7FA6M2AF3CFB#AA0 trades dual Ethernet for higher clock speed and CAN FD - making R5F564MLCDFC#V1 optimal for cost-sensitive industrial gateways needing concurrent Ethernet, USB, and CAN 2.0B.
Availability
R5F564MLCDFC#V1 is available at Aetrix Electronics and suitable for industrial PLCs, smart energy gateways, factory HMIs, and medical diagnostic interfaces requiring stable component supply across extended product lifecycles.
Supply support for R5F564MLCDFC#V1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, and power management ICs for industrial, automotive, and IoT applications.
The RX64M Group, including R5F564MLCDFC#V1, was designed for high-integrity industrial automation systems requiring deterministic real-time performance, multi-protocol connectivity, and built-in functional safety features.
FAQ
What is the maximum operating frequency and DMIPS rating of the R5F564MLCDFC#V1?
The R5F564MLCDFC#V1 operates at a maximum frequency of 120 MHz and delivers 240 DMIPS of processing performance. This is achieved through the RXv2 CPU core's 5-stage pipeline and optimized instruction set, enabling real-time deterministic execution for industrial control loops. The R5F564MLCDFC#V1 maintains this performance across its full operating temperature range (–40°C to +105°C) with no wait states on its 4 MB code flash memory.
Does the R5F564MLCDFC#V1 support IEEE 1588 Precision Time Protocol?
Yes, the R5F564MLCDFC#V1 integrates a dedicated PTP controller (EPTPC) compliant with IEEE 1588-2008, tightly coupled to both Ethernet MACs. It provides hardware timestamping with sub-100 ns resolution on transmit and receive frames, enabling precise time synchronization for distributed control systems. The R5F564MLCDFC#V1 supports one-step and two-step clock correction modes and can operate as master, slave, or boundary clock.
How many Ethernet MACs does the R5F564MLCDFC#V1 include, and what interfaces do they support?
The R5F564MLCDFC#V1 includes two fully independent IEEE 802.3-compliant Ethernet MACs (ETHERC), each supporting 10/100 Mbps full- and half-duplex operation. Both support MII and RMII physical layer interfaces, Magic Packet wake-on-LAN, IEEE 802.3x flow control, and multicast filtering. Each MAC has dedicated EDMAC channels and 4 KB receive / 2 KB transmit FIFOs - allowing concurrent high-bandwidth traffic without CPU overhead. The R5F564MLCDFC#V1 does not integrate PHYs; external PHYs must be used.
What analog peripherals are integrated into the R5F564MLCDFC#V1?
The R5F564MLCDFC#V1 integrates two 12-bit A/D converter units (S12ADC): Unit 0 with 8 channels and Unit 1 with 21 channels, supporting 8/10/12-bit resolution and 0.48 µs conversion time. It also includes two 12-bit D/A channels (R12DA) with selectable amplifier or direct output, and an on-chip temperature sensor with ±1°C relative precision. All analog blocks support self-diagnostic functions and event-triggered operation via the ELC - critical for IEC 60730 compliance in the R5F564MLCDFC#V1.
Is USB battery charging supported on the R5F564MLCDFC#V1?
Yes, the R5F564MLCDFC#V1 includes a dedicated USBA module with full-speed USB 2.0 support and integrated battery charging detection (BC 1.2 compliant). It supports DCP, CDP, and SDP charging modes and includes 8.5 KB of on-chip RAM for USB transfer buffering. This functionality is only available on 176-pin packages like the R5F564MLCDFC#V1 - not on smaller pin-count variants - and requires no external pull-up resistors.
R5F564MLCDFC#V1 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 176-LQFP
- Series:
- RX600
- Packaging:
- Tray
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Core Processor:
- RXv2
- Core Size:
- 32-Bit Single-Core
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, SCI, SPI, SSI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 127
- Program Memory Size:
- 4MB (4M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 64K x 8
- RAM Size:
- 552K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 29x12b; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F564MLCDFC#V1 FAQ
1.How can I place an order for R5F564MLCDFC#V1 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F564MLCDFC#V1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F564MLCDFC#V1 reliable?
The price and inventory of R5F564MLCDFC#V1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F564MLCDFC#V1 is usually 5 days.
3.What payment methods are accepted for R5F564MLCDFC#V1?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F564MLCDFC#V1 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F564MLCDFC#V1?
R5F564MLCDFC#V1 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F564MLCDFC#V1 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F564MLCDFC#V1?
For technical support, including R5F564MLCDFC#V1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F564MLCDFC#V1 requirements.
6.How does Aetrix verify that R5F564MLCDFC#V1 is sourced from the original manufacturer or authorized distributors?
All R5F564MLCDFC#V1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F564MLCDFC#V1 meets industry standards.
7.What is the process for return or replacement of R5F564MLCDFC#V1?
All R5F564MLCDFC#V1 units undergo pre-shipment inspection (PSI). If there is an issue with R5F564MLCDFC#V1, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F564MLCDFC#V1 part is unused and in its original packaging.
Return procedure for R5F564MLCDFC#V1:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R5F564MLCDFC#V1 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

