Renesas R5F564MLCGFP#V1
- Part No.:
- R5F564MLCGFP#V1
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 100-LQFP
- Datasheet:
-
R5F564MLCGFP#V1.pdf
- Description:
- IC MCU 32BIT 4MB FLASH 100LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:3,621
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
R5F564MLCGFP#V1 from Renesas is a 120-MHz 32-bit RXv2 core MCU with integrated FPU, 4 MB code flash, 512 KB SRAM, IEEE 1588-compliant dual Ethernet MAC, full-speed USB 2.0 with battery charging, CAN (3 channels), and 12-bit A/D (29 total channels). It targets industrial networking gateways requiring deterministic real-time control, secure firmware updates, and multi-protocol connectivity.
For engineers reviewing the R5F564MLCGFP#V1 datasheet, R5F564MLCGFP#V1 pinout, R5F564MLCGFP#V1 application, or R5F564MLCGFP#V1 equivalent, key selection criteria include its 176-pin LFBGA package, dual Ethernet + USB + CAN coexistence, 120 MHz real-time performance with 240 DMIPS, and IEC60730-ready safety features including self-diagnostic A/D and oscillation-stop detection.
Technical Context
The R5F564MLCGFP#V1 implements the RXv2 CPU core with CISC Harvard architecture, 5-stage pipeline, and variable-length instructions enabling ultra-compact code. It integrates dual independent clock domains: ICLK up to 120 MHz for CPU and high-speed peripherals (ETHERC, USBA, AES), and PCLKB up to 60 MHz for timers, A/D, and D/A.
Its peripheral subsystem includes three communication stacks-dual IEEE 1588 Ethernet controllers with EPTPC and EDMAC, one USBA module with 8.5 KB buffer supporting battery charging, and three ISO11898-1 CAN modules with 32 mailboxes each-enabling concurrent industrial protocol handling without external co-processors.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit, 120 MHz max, 240 DMIPS - enables hard real-time task scheduling in motion control and PLC applications. |
| Memory | 4 MB code flash (no wait states at 120 MHz), 512 KB SRAM, 64 KB data flash (100k erase cycles) - supports field-upgradable firmware and large runtime buffers. |
| Ethernet | Dual IEEE 1588-compliant MACs with MII/RMII, 10/100 Mbps, cut-through forwarding - delivers precise time synchronization for industrial automation networks. |
| USB | Full-speed USB 2.0 host/function with battery charging (USBA), 8.5 KB on-chip RAM - eliminates external PHY and supports direct device charging in embedded HMI. |
| CAN | 3 × ISO11898-1 compliant channels, 32 mailboxes per channel - handles multiple CAN FD-capable buses (e.g., J1939 + CANopen + proprietary) simultaneously. |
| A/D Converter | Two 12-bit units: S12AD0 (8 ch), S12AD1 (21 ch); 0.48 µs conversion time - captures fast analog transients in motor current sensing and power quality monitoring. |
| Package | LFBGA-176 (13 mm × 13 mm, 0.8 mm pitch, PLBG0176GA-A) - provides high I/O count (127 GPIO) with 5-V tolerant pins for legacy interface bridging. |
Pinout & Package
Package: PLBG0176GA-A, 176-pin Low-Profile Fine-Pitch Ball Grid Array (LFBGA), 13 mm × 13 mm, 0.8 mm pitch, RoHS-compliant, lead-free.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC, AVCC0, AVCC1 | Power supply inputs | Separate digital (VCC) and analog (AVCC0/AVCC1) rails enable noise isolation for precision A/D and RTC operation. |
| VBATT | Battery backup supply | Retains RTC and 8 KB standby RAM during main power loss - critical for timestamped event logging in energy meters. |
| ETXD0–ETXD3, ETXCK, ERXD0–ERXD3, ERXCK | Ethernet PHY interface (MII) | Direct connection to external Ethernet PHY without level-shifting - reduces BOM cost and layout complexity in gateway designs. |
| USBDP/USBDM | USB 2.0 differential data pair | Integrated transceiver supports full-speed signaling without external termination resistors - simplifies USB compliance testing. |
| TXDn/RXDn (SCIg/h) | Serial communication interfaces | 9 configurable SCI channels support UART, SPI, I²C, LIN, and smart-card modes - replaces discrete protocol translators in multi-interface systems. |
| AD00–AD28 | Analog input channels | 29 dedicated A/D inputs across two units with independent clock domains (PCLKC/PCLKD) - allows simultaneous sampling of motor phase currents and DC bus voltage. |
Key Features
| Feature | Design Value |
|---|---|
| IEC60730 Safety Support | Oscillation-stop detection, CRC calculation unit, IWDTa windowing, A/D self-diagnostic, register write protection - enables Class B certification without external safety monitors. |
| Real-Time Determinism | Fast interrupt response (≤12 cycles), ELC event linking, MTU3/GPT PWM with dead-time compensation - guarantees sub-microsecond jitter in servo drive PWM generation. |
| Cryptographic Acceleration | Hardware AES-128/192/256, DES/T-DES, SHA-1/224/256 - accelerates TLS handshake and firmware signature verification in under 10 ms. |
| Low-Power Operation | 0.3 mA/MHz typical active current, four low-power modes (deep software standby draws 1.5 µA) - extends battery life in wireless edge nodes with periodic wake-up. |
| Flexible Clock System | Dual PLLs, LOCO/HOCO/external crystal sources, independent PCLKA/PCLKB domains - allows dynamic clock scaling while maintaining Ethernet timing integrity. |
Applications
| Industrial Ethernet Gateway | Programmable Logic Controller (PLC) |
|---|---|
|
Use Scenario: Aggregating Modbus TCP, EtherNet/IP, and PROFINET traffic between factory floor devices and cloud SCADA. IC Role / Device Role / Timing Role: Dual Ethernet MAC + USBA + CAN controller acts as protocol translation hub with IEEE 1588 time stamping for synchronized I/O scanning. Use Value: Eliminates need for external FPGA or dual-MCU architecture; 120 MHz RXv2 core executes real-time packet inspection and routing in <50 µs. |
Use Scenario: Compact DIN-rail mounted PLC executing ladder logic with 32 I/O points, motion control, and HMI communication. IC Role / Device Role / Timing Role: Central controller managing 16-channel A/D acquisition, 4-channel D/A output, 3-axis GPT PWM generation, and SDHI-based program storage. Use Value: On-chip 512 KB SRAM stores ladder logic state tables; hardware CRC and self-test meet IEC61131-3 functional safety requirements. |
| Energy Meter with Secure Firmware Update | Motor Drive Control Unit |
|
Use Scenario: Smart electricity meter performing harmonic analysis, tamper detection, and OTA firmware updates over cellular backhaul. IC Role / Device Role / Timing Role: Security coprocessor (AES/SHA) validates signed firmware images; RTC with VBATT backup maintains accurate billing timestamps during outages. Use Value: Hardware crypto engine reduces update time by 70% vs. software-only; 12-bit A/D with disconnection detection identifies sensor faults before revenue loss. |
Use Scenario: 3-phase inverter controlling PMSM motors in HVAC compressors with field-oriented control (FOC). IC Role / Device Role / Timing Role: MTU3/GPT generate complementary PWM with programmable dead time; S12AD1 samples all three phase currents simultaneously via ELC-triggered conversion. Use Value: 0.48 µs A/D conversion enables 20 kHz PWM carrier frequency with precise current loop closure; POE3a prevents shoot-through during fault conditions. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F566TEADFP#30 | Same RX64M family, 144-pin LQFP, 2 MB flash, single Ethernet MAC, no USBA battery charging | Suitable for cost-sensitive PLCs without dual-network redundancy or USB peripheral support | Select when board space permits LQFP and dual Ethernet/USB is not required. |
| R7FA6M2AF3CFP#AA0 | RX72M family, 176-pin LFBGA, 120 MHz, 2 MB flash, single Ethernet, no hardware crypto, enhanced FPU | Optimized for motor control with higher FPU throughput but lacks IEC60730 safety features and dual Ethernet | Choose for FOC-intensive applications where cryptographic security is handled externally. |
Compared with R5F564MLCGFP#V1, R5F566TEADFP#30 offers lower BOM cost and simpler layout but sacrifices dual Ethernet redundancy and USB battery charging; R7FA6M2AF3CFP#AA0 delivers superior FPU performance for advanced motor algorithms but requires external security ICs for firmware validation and lacks IEEE 1588 hardware timestamping.
Availability
R5F564MLCGFP#V1 is available at Aetrix Electronics and suitable for industrial gateways, programmable logic controllers, smart energy meters, and motor drive control units requiring stable component supply across extended product lifecycles.
Supply support for R5F564MLCGFP#V1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader headquartered in Tokyo, Japan, specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.
The RX64M Group, including R5F564MLCGFP#V1, was designed specifically for industrial automation applications demanding real-time determinism, functional safety compliance (IEC60730), and multi-protocol connectivity in a single chip.
FAQ
What is the maximum operating frequency and core type of the R5F564MLCGFP#V1?
The R5F564MLCGFP#V1 operates at a maximum frequency of 120 MHz using the 32-bit RXv2 CPU core. This core delivers 240 DMIPS performance and includes a single-precision IEEE-754 floating-point unit, two multiply-and-accumulate units, and a 5-stage pipeline with variable-length instructions for compact code density. The R5F564MLCGFP#V1 achieves deterministic real-time execution essential for industrial control loops.
Does the R5F564MLCGFP#V1 support IEEE 1588 Precision Time Protocol?
Yes, the R5F564MLCGFP#V1 integrates a dedicated PTP controller (EPTPC) linked to both Ethernet MACs, providing hardware timestamping compliant with IEEE 1588-2008. It supports one-step and two-step clock synchronization, transparent clock functionality, and hardware-assisted correction of residence time in switches - enabling sub-microsecond time accuracy in industrial Ethernet networks without external timing ICs.
What are the memory resources available on the R5F564MLCGFP#V1?
The R5F564MLCGFP#V1 includes 4 MB of on-chip code flash memory with zero wait-state access at 120 MHz, 512 KB of general-purpose SRAM, 64 KB of reprogrammable data flash rated for 100,000 erase cycles, 32 KB of ECC-protected RAM, and 8 KB of battery-backed standby RAM. These resources support complex real-time OS environments, secure firmware updates, and long-duration data logging - all within the R5F564MLCGFP#V1 die.
How many communication interfaces does the R5F564MLCGFP#V1 support?
The R5F564MLCGFP#V1 supports dual IEEE 1588-compliant Ethernet MACs, one full-speed USB 2.0 host/function interface with battery charging capability (USBA), three ISO11898-1 CAN modules (32 mailboxes each), nine SCI channels (UART/SPI/I²C/LIN), four SCIFA interfaces with 16-byte FIFOs, two I²C buses (up to 1 Mbps), one QSPI, one SD host interface, and one MMCIF. This comprehensive set enables concurrent multi-protocol operation in industrial edge devices without external bridge ICs.
Is the R5F564MLCGFP#V1 qualified for functional safety standards?
Yes, the R5F564MLCGFP#V1 includes hardware features required for IEC60730 Class B compliance: oscillation-stop detection, hardware CRC calculator, windowed independent watchdog timer (IWDTa), A/D converter self-diagnostic function, and register write protection. These capabilities are documented in Renesas' Functional Safety Manual R01UM0077EJ0200 and allow system-level certification without adding external safety monitors - a key advantage of the R5F564MLCGFP#V1 in safety-critical applications.
R5F564MLCGFP#V1 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 100-LQFP
- Series:
- RX
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv2
- Core Size:
- 32-Bit
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, SCI, SPI, SSI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 78
- Program Memory Size:
- 4MB (4M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 64K x 8
- RAM Size:
- 512K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 29x12b; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F564MLCGFP#V1 FAQ
1.How can I place an order for R5F564MLCGFP#V1 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F564MLCGFP#V1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F564MLCGFP#V1 reliable?
The price and inventory of R5F564MLCGFP#V1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F564MLCGFP#V1 is usually 5 days.
3.What payment methods are accepted for R5F564MLCGFP#V1?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F564MLCGFP#V1 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F564MLCGFP#V1?
R5F564MLCGFP#V1 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F564MLCGFP#V1 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F564MLCGFP#V1?
For technical support, including R5F564MLCGFP#V1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F564MLCGFP#V1 requirements.
6.How does Aetrix verify that R5F564MLCGFP#V1 is sourced from the original manufacturer or authorized distributors?
All R5F564MLCGFP#V1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F564MLCGFP#V1 meets industry standards.
7.What is the process for return or replacement of R5F564MLCGFP#V1?
All R5F564MLCGFP#V1 units undergo pre-shipment inspection (PSI). If there is an issue with R5F564MLCGFP#V1, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F564MLCGFP#V1 part is unused and in its original packaging.
Return procedure for R5F564MLCGFP#V1:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R5F564MLCGFP#V1 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

