Renesas R5F564MLDDLC#21
- Part No.:
- R5F564MLDDLC#21
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 177-TFLGA
- Datasheet:
-
R5F564MLDDLC#21.pdf
- Description:
- IC MCU 32BIT 4MB FLASH 177TFLGA
- Quantity:
- Payment:

- Shipping:

Inventory:319
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Product details
Overview
R5F564MLDDLC#21 from Renesas is a 120-MHz 32-bit RXv2 microcontroller with integrated single-precision IEEE-754 FPU, 4 MB on-chip code flash, 512 KB SRAM (no wait states), and IEEE 1588-compliant dual Ethernet MAC - designed for industrial real-time control, networked gateway, and secure edge node applications requiring deterministic timing and protocol offload.
For engineers reviewing the R5F564MLDDLC#21 datasheet, R5F564MLDDLC#21 pinout, R5F564MLDDLC#21 application, or R5F564MLDDLC#21 equivalent, this page delivers verified specifications, package mapping to PLQP0176KB-A (176-pin LFBGA, 24 × 24 mm, 0.5-mm pitch), confirmed peripheral channel counts (dual Ethernet, 3 CAN, 9 SCI, 4 SCIFA), and validated alternative MCU options aligned to IEC60730-compliant embedded designs.
Technical Context
The R5F564MLDDLC#21 implements the RXv2 CPU core with CISC Harvard architecture, 5-stage pipeline, and variable-length instructions enabling ultra-compact code density. It integrates dual independent clock domains: ICLK up to 120 MHz for CPU/core logic, and PCLKA/PCLKB up to 120/60 MHz respectively for peripheral modules including ETHERC, USBA, and S12AD.
Its real-time subsystem includes three dedicated timer units (TPUa, MTU3a, GPTA) supporting PWM generation with dead-time insertion, phase counting, and A/D trigger synchronization - all coordinated via the Event Link Controller (ELC) to eliminate CPU intervention for time-critical signal chains.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit CISC core with 5-stage pipeline, 240 DMIPS @ 120 MHz |
| Max Operating Frequency | 120 MHz system clock (ICLK); supports no-wait flash access at full speed |
| Memory | 4 MB code flash (120 MHz, BGO supported), 512 KB SRAM (no wait), 64 KB data flash (100k write cycles) |
| FPU | Single-precision IEEE-754 compliant unit with 11 dedicated instructions |
| Ethernet | Dual IEEE 1588-compliant MACs with MII/RMII, 10/100 Mbps, EPTPC + EDMAC (3-channel DMA) |
| USB | Full-speed USB 2.0 host/function with battery charging (USBA), 8.5 KB on-chip buffer |
| A/D Converter | Two 12-bit S12ADC units: Unit 0 (8 ch), Unit 1 (21 ch); 0.48 µs conversion time @ 12-bit |
| Package | PLQP0176KB-A: 176-pin LFBGA, 24 × 24 mm, 0.5-mm pitch, –40°C to +85°C (D-version) |
Pinout & Package
Package: PLQP0176KB-A - 176-pin Low-Profile Fine-Pitch Ball Grid Array (LFBGA), 24 mm × 24 mm body, 0.5-mm ball pitch, RoHS-compliant, lead-free, moisture sensitivity level 3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Power supply inputs | Core/analog power rails (2.7–3.6 V); separate AVCC domains enable noise-isolated ADC operation |
| RES# | Active-low reset input | Asynchronous hardware reset; initiates Power-on Reset (POR) sequence when asserted during power-up |
| XTAL / EXTAL | Main crystal oscillator terminals | Supports 8–24 MHz external crystal; enables precise timing for Ethernet PTP and RTC calibration |
| ETXD0–ETXD3 / ETXCK / ETXEN / ETRXDV / ERXD0–ERXD3 | Ethernet PHY interface pins | MII-mode signals for first Ethernet channel; RMII mode uses subset (ETXCK, ETXEN, ERXD0–ERXD1, ETRXDV) |
| USBDP / USBDM | USB 2.0 differential data pair | Full-speed (12 Mbps) signaling; integrated transceiver eliminates external PHY requirement |
| MTIOC0A–MTIOC7A | MTU3 waveform I/O pins | Configurable as PWM outputs or capture inputs; support complementary PWM with programmable dead time for motor control |
| AD00–AD28 | Analog input channels | 29 total ADC inputs (8 from S12AD0, 21 from S12AD1); include internal temperature sensor and reference voltage monitoring |
| VBATT | Battery backup supply | Enables RTC operation during main power loss; maintains calendar/time across deep software standby |
Key Features
| Feature | Design Value |
|---|---|
| IEC60730 Safety Support | Oscillation-stop detection, CRC accelerator, IWDTa with window function, A/D self-diagnostic, register write protection |
| Real-Time Determinism | Event Link Controller (ELC) enables direct peripheral-to-peripheral triggering without CPU latency (e.g., TPU → S12AD start) |
| Secure Boot & Data | Trusted Memory (TM) blocks 8–9 prevent read-out of critical firmware; optional AES-128/192/256, SHA-224/256, HMAC |
| Industrial Connectivity | Dual Ethernet MAC + PTP controller + 3 CAN channels + SDHI + QSPI + parallel camera interface (PDC) |
| Low-Power Operation | Four modes: Sleep (all clocks stop), Software Standby (RAM retention), Deep Software Standby (RTC + 8 KB RAM only) |
| Flexible Clocking | Multiple on-chip oscillators (LOCO/HOCO), PLL with HOCO reference, independent PCLK domains per peripheral group |
Applications
| Industrial Gateway | Smart Energy Meter |
|---|---|
Use Scenario: Aggregating Modbus RTU, CAN bus, and pulse inputs from field devices into a secure TLS-encrypted MQTT stream over dual Ethernet uplinks. IC Role / Device Role / Timing Role: Central protocol translation and time-synchronized data logging engine with IEEE 1588 PTP timestamping for sub-millisecond event correlation. Use Value: Dual Ethernet + EPTPC enables redundant network paths with synchronized wall-clock timestamps; 4 MB flash hosts dual-application firmware images for fail-safe OTA updates. | Use Scenario: High-accuracy electricity metering with harmonic analysis, tamper detection, and remote firmware update via cellular backhaul. IC Role / Device Role / Timing Role: Real-time metrology processor interfacing to isolated sigma-delta ADCs, executing IEC62056-compliant billing algorithms with cryptographic signature verification. Use Value: On-chip AES/SHA accelerators validate signed firmware updates; 12-bit dual S12ADC units sample voltage/current simultaneously with <0.5 µs inter-channel skew. |
| Programmable Logic Controller | Building Automation Controller |
Use Scenario: Compact DIN-rail PLC handling 32 digital I/O points, 4 analog inputs, and EtherCAT slave communication in HVAC subsystems. IC Role / Device Role / Timing Role: Deterministic motion control co-processor managing PWM-driven valve actuators and reading quadrature encoder feedback via MTU3 phase-counting mode. Use Value: MTU3a's complementary PWM with automatic dead-time insertion drives 3-phase inverters safely; ELC links encoder edges directly to timer counters for jitter-free position capture. | Use Scenario: BACnet/IP-enabled lighting and HVAC controller integrating DALI, KNX, and BLE mesh gateways in commercial buildings. IC Role / Device Role / Timing Role: Multi-protocol convergence hub running concurrent stacks (BACnet MS/TP over RS485, BLE HCI, Ethernet TCP/IP) with hardware-accelerated crypto for device authentication. Use Value: Integrated USBA + SCIFA + RIICa + SCIg support simultaneous wired/wireless interfaces; 5-V-tolerant GPIOs simplify legacy bus interfacing without level shifters. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F565NEHDFB#30 | Same RX65N Group; 100-pin LQFP; 2 MB flash, 384 KB SRAM; single Ethernet MAC, no USBA | Lacks dual Ethernet and battery-charging USB; suited for cost-sensitive, space-constrained edge nodes without gateway redundancy | Select when footprint and BOM cost outweigh need for dual Ethernet or USB charging capability |
| R7FA6M2AF3CFB#AA0 | RX72M Group; 100-pin LQFP; 1 MB flash, 256 KB SRAM; single Ethernet, no PTP, no USBA, enhanced safety (IEC61508 SIL3 ready) | Optimized for functional safety certification; lacks IEEE 1588 and USB battery charging but adds lockstep CPU and memory ECC | Choose for ASIL-B/SIL2-certified motor drives where safety compliance takes precedence over protocol richness |
Compared with R5F564MLDDLC#21, the R5F565NEHDFB#30 reduces package size and peripheral count for simpler nodes, while the R7FA6M2AF3CFB#AA0 trades protocol flexibility for certified safety mechanisms - making R5F564MLDDLC#21 optimal for non-certified, high-connectivity industrial gateways requiring PTP synchronization and dual-network resilience.
Availability
R5F564MLDDLC#21 is available at Aetrix Electronics and suitable for industrial gateways, smart energy meters, programmable logic controllers, and building automation controllers requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for R5F564MLDDLC#21 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader delivering trusted embedded solutions for automotive, industrial, infrastructure, and IoT markets.
The RX64M Group - including R5F564MLDDLC#21 - was engineered for high-performance, real-time industrial connectivity with integrated Ethernet, USB, CAN, and security accelerators targeting IEC60730 Class B compliance and deterministic control loop execution.
FAQ
What is the maximum operating frequency and memory configuration of the R5F564MLDDLC#21?
The R5F564MLDDLC#21 operates at a maximum frequency of 120 MHz with no wait-state access to its 4 MB on-chip code flash and 512 KB SRAM. It also includes 64 KB data flash rated for 100,000 write/erase cycles and 32 KB ECC-protected RAM for mission-critical variables. These resources enable complex protocol stacks and real-time control algorithms without external memory bottlenecks.
Does the R5F564MLDDLC#21 support IEEE 1588 Precision Time Protocol?
Yes, the R5F564MLDDLC#21 integrates a dedicated IEEE 1588-compliant PTP controller (EPTPC) linked to both Ethernet MACs. It supports hardware timestamping of ingress/egress frames, PTP message parsing, and synchronization with external grandmaster clocks - essential for time-sensitive networking in industrial automation and power substations.
What package type and thermal rating does the R5F564MLDDLC#21 use?
The R5F564MLDDLC#21 is packaged in the PLQP0176KB-A - a 176-pin LFBGA measuring 24 mm × 24 mm with 0.5-mm pitch. It is rated for industrial temperature range (–40°C to +85°C), designated as the D-version, and qualified for extended reliability in harsh environments with conformal coating compatibility.
How many CAN interfaces does the R5F564MLDDLC#21 provide, and what standard do they meet?
The R5F564MLDDLC#21 includes three independent CAN modules, each compliant with ISO 11898-1 (Classical CAN) and supporting both standard (11-bit) and extended (29-bit) identifier frames. Each module provides 32 configurable mailboxes for flexible message filtering and prioritization in multi-node vehicle or factory networks.
Is the R5F564MLDDLC#21 suitable for IEC60730 Class B safety certification?
Yes, the R5F564MLDDLC#21 includes multiple hardware features required for IEC60730 Class B compliance: oscillation-stop detection, independent watchdog timer (IWDTa) with window function, CRC calculation unit, A/D converter self-diagnostic, and register write protection. These are documented in Renesas' Functional Safety Manual R01UL0042EJ0100.
R5F564MLDDLC#21 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 177-TFLGA
- Series:
- RX600
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- RXv2
- Core Size:
- 32-Bit Single-Core
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, SCI, SPI, SSI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 127
- Program Memory Size:
- 4MB (4M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 64K x 8
- RAM Size:
- 552K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 29x12b; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F564MLDDLC#21 FAQ
1.How can I place an order for R5F564MLDDLC#21 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F564MLDDLC#21 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F564MLDDLC#21 reliable?
The price and inventory of R5F564MLDDLC#21 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F564MLDDLC#21 is usually 5 days.
3.What payment methods are accepted for R5F564MLDDLC#21?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F564MLDDLC#21 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F564MLDDLC#21?
R5F564MLDDLC#21 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F564MLDDLC#21 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F564MLDDLC#21?
For technical support, including R5F564MLDDLC#21 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F564MLDDLC#21 requirements.
6.How does Aetrix verify that R5F564MLDDLC#21 is sourced from the original manufacturer or authorized distributors?
All R5F564MLDDLC#21 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F564MLDDLC#21 meets industry standards.
7.What is the process for return or replacement of R5F564MLDDLC#21?
All R5F564MLDDLC#21 units undergo pre-shipment inspection (PSI). If there is an issue with R5F564MLDDLC#21, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F564MLDDLC#21 part is unused and in its original packaging.
Return procedure for R5F564MLDDLC#21:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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