Renesas R5F564MLGDBG#21
- Part No.:
- R5F564MLGDBG#21
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 176-LFBGA
- Datasheet:
-
R5F564MLGDBG#21.pdf
- Description:
- IC MCU 32BIT 4MB FLASH 176LFBGA
- Quantity:
- Payment:

- Shipping:

Inventory:304
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Product details
Overview
R5F564MLGDBG#21 from Renesas is a 120-MHz 32-bit RXv2 microcontroller with integrated FPU, 4 MB on-chip code flash, 512 KB SRAM, IEEE 1588-compliant dual Ethernet MAC, full-speed USB 2.0 with battery charging support, and CAN 2.0B - deployed in industrial gateways requiring deterministic real-time control, secure connectivity, and multi-protocol edge processing.
For engineers reviewing the R5F564MLGDBG#21 datasheet, R5F564MLGDBG#21 pinout, R5F564MLGDBG#21 application, or R5F564MLGDBG#21 equivalent, key selection considerations include its 177-pin TFLGA package (8 × 8 mm, 0.5-mm pitch), dual-channel Ethernet with PTP hardware timestamping, 21-channel 12-bit ADC unit, 32 KB ECC-protected RAM, and IEC60730 safety features including self-diagnostic A/D and oscillation-stop detection.
Technical Context
The R5F564MLGDBG#21 implements the RXv2 CPU core with 240 DMIPS performance at 120 MHz, single-precision IEEE-754 FPU, and dual multiply-accumulate units - enabling real-time signal processing in motor control and audio applications. Its clock system integrates PLL, HOCO (16/18/20 MHz), LOCO (240 kHz), and IWDT-dedicated oscillator for independent watchdog timing.
Peripheral architecture includes three communication domains: PCLKA-synchronized modules (Ethernet, USB, AES, RSPI) running up to 120 MHz; PCLKB-synchronized peripherals (timers, SCIg/h, RIIC) up to 60 MHz; and separate ADCLK domains (PCLKC/PCLKD) for dual 12-bit ADC units - ensuring precise timing isolation for mixed-signal acquisition and control loops.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit CISC Harvard with 5-stage pipeline, 240 DMIPS @ 120 MHz |
| Flash Memory | 4 MB code flash, zero-wait-state access at 120 MHz, background programming/erasing |
| RAM | 512 KB SRAM (no wait), 32 KB ECC-protected RAM (SEC-DED), 8 KB standby RAM |
| ADC | Dual 12-bit S12ADC: Unit 0 (8 ch), Unit 1 (21 ch); 0.48 µs conversion time per channel |
| Ethernet | Dual IEEE 1588-compliant MAC with EPTPC hardware timestamping and EDMAC DMA channels |
| USB | Full-speed USB 2.0 host/function with battery charging support, 8.5 KB on-chip buffer |
| Package | TFLGA-177 (8 × 8 mm, 0.5-mm pitch), G-grade (–40°C to +105°C) |
Pinout & Package
Package: TFLGA-177 (8 × 8 mm, 0.5-mm pitch), lead-free, RoHS-compliant, G-grade temperature range (–40°C to +105°C).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Power supply inputs | Separate digital/analog supplies enable noise isolation for ADC and analog peripherals |
| XTAL / EXTAL | Main crystal oscillator terminals | Supports 8–24 MHz external resonator for high-accuracy system clock generation |
| VBATT | Battery backup supply | Enables RTC operation during main power loss without external circuitry |
| ETH_MDC / ETH_MDIO | MDIO management interface | IEEE 802.3-compliant PHY configuration and status monitoring for both Ethernet channels |
| USBA_VBUS / USBA_DP / USBA_DM | USB 2.0 FS transceiver pins | Integrated transceiver with battery charging detection (BC1.2 compliant) eliminates external PHY |
| CAN0_TX / CAN0_RX / CAN1_TX / CAN1_RX / CAN2_TX / CAN2_RX | CAN bus interfaces | Three independent ISO 11898-1 compliant CAN controllers with 32 mailboxes each |
Key Features
| Feature | Design Value |
|---|---|
| IEC60730 Safety Support | Hardware CRC, oscillation-stop detection, A/D self-diagnostic, register write protection for functional safety certification |
| Real-Time Determinism | Fast interrupt response (<100 ns), event link controller (ELC) enables CPU-free peripheral interoperation |
| Secure Boot & Encryption | AES-128/192/256, DES/TDES, SHA-1/224/256/HMAC with trusted memory (TM) protecting flash blocks 8–9 |
| Multi-Protocol Connectivity | Dual Ethernet + USB + CAN + SDHI + QSPI + dual I²C + 9× SCI + 2× SSI - all concurrently operable |
| Low-Power Operation | 0.3 mA/MHz typical active current; four low-power modes including deep software standby with RTC retention |
Applications
| Industrial Gateway | Smart Energy Meter |
|---|---|
Use Scenario: Edge node aggregating Modbus TCP, CANopen, and MQTT data from field devices into cloud-uplink via dual Ethernet. IC Role / Device Role / Timing Role: Central controller executing protocol translation, real-time scheduling, and secure TLS offload using on-chip AES. Use Value: Dual IEEE 1588 Ethernet enables synchronized time-stamping across distributed sensors; 21-channel ADC supports simultaneous voltage/current/temperature sampling. | Use Scenario: DIN-rail mounted meter performing harmonic analysis, tamper detection, and encrypted firmware updates over cellular backhaul. IC Role / Device Role / Timing Role: Safety-certified MCU managing metrology engine (S12ADC), secure boot, and IEC60730 Class B compliance checks. Use Value: A/D self-diagnostic and register write protection satisfy Class B requirements; 32 KB ECC RAM ensures integrity of critical calibration data. |
| Motor Drive Controller | Audio Processing Node |
Use Scenario: Closed-loop servo drive with field-oriented control (FOC), encoder feedback, and CAN-based motion coordination. IC Role / Device Role / Timing Role: Real-time executor of FOC algorithms using RXv2 FPU and MTU3/GPT PWM timers with dead-time compensation. Use Value: Complementary PWM output mode generates non-overlapping gate signals; 120 MHz CPU delivers <1 µs current loop update time. | Use Scenario: Voice-enabled HMI with echo cancellation, audio codec interfacing, and local speech recognition inference. IC Role / Device Role / Timing Role: Audio subsystem manager handling I²S/SSI data streams, SRC sample-rate conversion, and DSP acceleration via FPU. Use Value: Dual SSI interfaces support simultaneous microphone array input and speaker output; SRC enables flexible clock domain bridging between codecs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F565NEGDBG#21 | Same RX64M family, 177-pin TFLGA, but 2.5 MB flash, no USB battery charging support | Lacks USBA module with BC1.2 detection; suitable where USB host charging is not required | Select when lower code density suffices and cost optimization is prioritized over USB charging capability |
| R5F566TEADFP#30 | RX66T group, 144-pin LQFP, 1.2 GHz equivalent performance, enhanced PWM timers for motor control | Optimized for high-speed motor control (e.g., inverters), lacks dual Ethernet and SDHI | Prefer for servo drives needing >200 kHz PWM carrier frequency; not drop-in due to different pinout and peripheral set |
Compared with R5F564MLGDBG#21, R5F565NEGDBG#21 reduces flash capacity and omits USB battery charging while retaining identical package and Ethernet capability - making it viable for cost-sensitive gateways without charging needs; R5F566TEADFP#30 shifts focus to motor control with higher PWM resolution and frequency, sacrificing dual Ethernet and SD storage support.
Availability
R5F564MLGDBG#21 is available at Aetrix Electronics and suitable for industrial gateways, smart energy meters, motor drive controllers, and audio processing nodes requiring stable component supply across extended product lifecycles.
Supply support for R5F564MLGDBG#21 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader delivering trusted embedded solutions for automotive, industrial, infrastructure, and IoT markets.
The RX64M Group targets high-performance industrial automation and networking applications - combining real-time determinism, functional safety features, and multi-protocol connectivity in a single-chip solution.
FAQ
What is the maximum operating frequency and CPU architecture of the R5F564MLGDBG#21?
The R5F564MLGDBG#21 operates at a maximum frequency of 120 MHz using the 32-bit RXv2 CPU core. It delivers 240 DMIPS performance and includes a single-precision IEEE-754 floating-point unit, two multiply-accumulate units, and a 5-stage pipeline Harvard architecture. This architecture enables deterministic real-time execution essential for industrial control and communication stacks in the R5F564MLGDBG#21.
Does the R5F564MLGDBG#21 support IEEE 1588 Precision Time Protocol?
Yes, the R5F564MLGDBG#21 includes a dedicated PTP controller (EPTPC) tightly coupled to its dual Ethernet MAC modules, providing hardware timestamping compliant with IEEE 1588-2008. This allows sub-microsecond time synchronization across distributed nodes - critical for time-sensitive networking in industrial automation systems implemented with the R5F564MLGDBG#21.
What are the memory resources available on the R5F564MLGDBG#21?
The R5F564MLGDBG#21 integrates 4 MB of on-chip code flash memory with zero-wait-state operation at 120 MHz, 64 KB of reprogrammable data flash (100,000 erase/write cycles), 512 KB of general-purpose SRAM, 32 KB of ECC-protected RAM (SEC-DED), and 8 KB of battery-backed standby RAM. These memory resources support complex firmware, secure boot, and real-time data buffering in demanding applications of the R5F564MLGDBG#21.
Which communication interfaces does the R5F564MLGDBG#21 support for industrial networking?
The R5F564MLGDBG#21 supports dual IEEE 802.3-compliant Ethernet MACs with MII/RMII, full-speed USB 2.0 with battery charging (USBA), three CAN 2.0B controllers (32 mailboxes each), SD host interface (SDHI), quad SPI (QSPI), two I²C buses (up to 1 Mbps), nine SCI channels, and two serial sound interfaces (SSI). This comprehensive suite enables robust multi-protocol industrial networking in the R5F564MLGDBG#21.
Is the R5F564MLGDBG#21 qualified for functional safety standards like IEC60730?
Yes, the R5F564MLGDBG#21 includes hardware features required for IEC60730 Class B compliance: oscillation-stop detection, hardware CRC calculation unit, self-diagnostic A/D converter, independent watchdog timer (IWDTa) with window function, and register write protection. These capabilities are documented in the R5F564MLGDBG#21 datasheet and enable certified safety firmware implementation without external components.
R5F564MLGDBG#21 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 176-LFBGA
- Series:
- RX600
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- RXv2
- Core Size:
- 32-Bit Single-Core
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, SCI, SPI, SSI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 127
- Program Memory Size:
- 4MB (4M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 64K x 8
- RAM Size:
- 552K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 29x12b; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F564MLGDBG#21 FAQ
1.How can I place an order for R5F564MLGDBG#21 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F564MLGDBG#21 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F564MLGDBG#21 reliable?
The price and inventory of R5F564MLGDBG#21 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F564MLGDBG#21 is usually 5 days.
3.What payment methods are accepted for R5F564MLGDBG#21?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F564MLGDBG#21 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F564MLGDBG#21?
R5F564MLGDBG#21 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F564MLGDBG#21 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F564MLGDBG#21?
For technical support, including R5F564MLGDBG#21 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F564MLGDBG#21 requirements.
6.How does Aetrix verify that R5F564MLGDBG#21 is sourced from the original manufacturer or authorized distributors?
All R5F564MLGDBG#21 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F564MLGDBG#21 meets industry standards.
7.What is the process for return or replacement of R5F564MLGDBG#21?
All R5F564MLGDBG#21 units undergo pre-shipment inspection (PSI). If there is an issue with R5F564MLGDBG#21, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F564MLGDBG#21 part is unused and in its original packaging.
Return procedure for R5F564MLGDBG#21:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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