Renesas R5F564MLGDFB#31
- Part No.:
- R5F564MLGDFB#31
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 144-LQFP
- Datasheet:
-
R5F564MLGDFB#31.pdf
- Description:
- IC MCU 32BIT 4MB FLASH 144LQFP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
R5F564MLGDFB#31 from Renesas is a 32-bit RXv2 core microcontroller operating at up to 120 MHz (240 DMIPS), featuring 4 MB on-chip code flash, 512 KB SRAM, IEEE 1588-compliant dual Ethernet MAC, full-speed USB 2.0 with battery charging support, and integrated 12-bit A/D and D/A converters - deployed in industrial automation gateways requiring real-time deterministic control, secure connectivity, and multi-protocol I/O.
For engineers reviewing the R5F564MLGDFB#31 datasheet, R5F564MLGDFB#31 pinout, R5F564MLGDFB#31 application, or R5F564MLGDFB#31 equivalent, this MCU delivers verified dual Ethernet timing synchronization, hardware-accelerated AES/SHA encryption, and configurable low-power modes for long-life embedded deployments where functional safety (IEC60730) compliance and peripheral integration are critical selection criteria.
Technical Context
The R5F564MLGDFB#31 implements the RXv2 CPU core with single-precision IEEE-754 FPU, two MAC units, and 32-bit multiplier/divider - enabling deterministic real-time math for motor control and signal processing. Its clock system supports independent domain scaling: ICLK up to 120 MHz, PCLKA up to 120 MHz (for Ethernet, USB, AES), and PCLKB up to 60 MHz (for timers, ADC, UART).
It integrates dual ETHERC modules with EPTPC (IEEE 1588 PTP), three CAN channels (ISO 11898-1), and USBA with 8.5 KB buffer - all mapped to dedicated DMA channels (EDMACa: 3 channels, DMACa: 8 channels, EXDMACa: 2 channels). The device uses PLQP0176KB-A package (176-pin LFBGA, 24 × 24 mm, 0.5-mm pitch) with 127 GPIOs, 19 of which are 5-V tolerant.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit CISC Harvard architecture with 5-stage pipeline, 240 DMIPS @ 120 MHz |
| Memory | 4 MB code flash (no wait states @ 120 MHz), 64 KB data flash (100k write cycles), 512 KB SRAM (no wait), 32 KB ECC RAM, 8 KB standby RAM |
| Real-Time Clock | RTCd with calendar, alarm, periodic interrupt, time-capture, and battery backup via VBATT pin |
| Analog Peripherals | Two 12-bit S12ADC units (8 + 21 channels), 2-channel R12DA with amplifier/direct output, on-die temperature sensor (±1°C) |
| Communication | Dual IEEE 1588 Ethernet MAC (MII/RMII), USBA with battery charging (8.5 KB buffer), 3× CAN, 9× SCIg/h, 4× SCIFA, 2× RIIC, QSPI, SDHI, SSI, SRC |
| Security & Safety | AES-128/192/256, DES/T-DES, SHA-1/224/256, HMAC, CRC, oscillation-stop detection, A/D self-diagnostic, register write protection |
| Power & Temp | 2.7–3.6 V supply, 0.3 mA/MHz typical active current, four low-power modes, –40°C to +105°C (G-version) |
Pinout & Package
Package: PLQP0176KB-A - 176-pin Low-Profile Fine-Pitch Ball Grid Array (LFBGA), 24 × 24 mm body, 0.5-mm ball pitch, RoHS-compliant, lead-free.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Core & analog power supply | Separate 2.7–3.6 V domains for digital logic and analog peripherals; decoupling required per datasheet layout guidelines |
| VBATT | Battery backup input | Supplies RTC during main power loss; enables calendar retention and wake-on-event without external circuitry |
| XTAL / EXTAL | Main crystal oscillator interface | Supports 8–24 MHz external crystal; enables precise timing for Ethernet PTP, USB, and real-time control loops |
| ETXD0–7 / ERXD0–7 | Ethernet PHY data bus | 8-bit MII interface per channel; supports dual 10/100 Mbps full/half-duplex operation with cut-through forwarding |
| USBDP / USBDM | USB 2.0 full-speed differential pair | Integrated transceiver with on-chip termination; no external resistors needed; supports host/function/OTG with battery charging |
| CANH / CANL | CAN bus differential outputs | Three independent ISO 11898-1 compliant CAN controllers; each with 32 mailboxes for prioritized message handling |
Key Features
| Feature | Design Value |
|---|---|
| IEEE 1588 Precision Time Protocol | Hardware-accelerated timestamping in EPTPC block synchronized to dual Ethernet MACs for sub-microsecond time alignment across distributed nodes |
| Background Operation (BGO) | Simultaneous code/data flash programming/erasing while executing application code - eliminates runtime interruption for firmware updates |
| Event Link Controller (ELC) | 119 internal event signals routed without CPU intervention - enables deterministic timer-triggered ADC sampling, PWM dead-time insertion, or GPIO toggling |
| IEC60730 Class B Support | Integrated self-test features: oscillation-stop detection, CRC engine, IWDTa windowed watchdog, A/D converter diagnostic, and register lock protection |
| Flexible Clock Domain Control | Independent frequency synthesis for ICLK, PCLKA/B/C/D, FCLK, and BCLK - allows optimal power/performance trade-offs per peripheral subsystem |
Applications
| Industrial Ethernet Gateway | Secure PLC Communication Module |
|---|---|
Use Scenario: Aggregating Modbus TCP, EtherNet/IP, and PROFINET traffic between field devices and cloud SCADA systems. IC Role / Device Role / Timing Role: Dual Ethernet MAC with IEEE 1588 PTP serves as time-synchronized packet forwarder and protocol translator. Use Value: Hardware timestamping eliminates software jitter; 4 MB flash stores multiple protocol stacks; AES/SHA secures firmware OTA updates. |
Use Scenario: Adding encrypted CAN-to-Ethernet bridging in programmable logic controllers with functional safety requirements. IC Role / Device Role / Timing Role: Real-time co-processor managing deterministic CAN messaging, watchdog supervision, and safe boot validation. Use Value: IEC60730-compliant self-tests ensure runtime integrity; 32 mailbox CAN buffers prevent message loss under heavy load; 127 GPIOs interface with I/O expansion modules. |
| Smart Energy Meter Hub | Multi-Protocol Building Controller |
Use Scenario: Collecting AMI data from RS485 (Modbus), M-Bus, and pulse inputs while reporting via Ethernet or cellular backhaul. IC Role / Device Role / Timing Role: High-resolution 12-bit A/D with disconnection detection monitors metering sensors; RTC maintains billing timestamps across power outages. Use Value: 8 KB standby RAM preserves meter logs during brownouts; SDHI supports local data logging; temperature sensor compensates ADC drift. |
Use Scenario: Central HVAC controller integrating BACnet MS/TP (via SCI), KNX (via UART), DALI lighting, and Ethernet management. IC Role / Device Role / Timing Role: Multi-protocol bridge with concurrent SCIg/SCIFA/RIIC/QSPI interfaces - routing commands between legacy and modern building systems. Use Value: 9 SCI channels eliminate external UART expanders; QSPI boots from external flash; 5-V tolerant GPIOs directly drive legacy 24 V control signals. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-performance industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F565NEHDFB#31 | Same RX64M group, 2.5 MB flash, 384 KB SRAM, no USBA (only USBb), single Ethernet MAC, 144-pin LFBGA | Suitable for cost-sensitive edge nodes without dual Ethernet or battery charging USB | Select when dual Ethernet and USB battery charging are not required; lower memory footprint reduces BOM cost |
| R5F571MLGDFB#31 | RX71M group, 120 MHz, 4 MB flash, 512 KB SRAM, same pinout, adds 2D graphics accelerator and JPEG codec | Targeted at HMI-enabled gateways needing local display rendering or image capture | Choose only if GUI/video processing is required; otherwise R5F564MLGDFB#31 offers identical real-time control and networking at lower power |
Compared with R5F564MLGDFB#31, R5F565NEHDFB#31 reduces Ethernet and USB capability for compact deployment, while R5F571MLGDFB#31 extends multimedia functionality without improving core real-time determinism or security acceleration - making R5F564MLGDFB#31 optimal for pure industrial connectivity and control.
Availability
R5F564MLGDFB#31 is available at Aetrix Electronics and suitable for industrial automation gateways, smart energy infrastructure, functional safety PLC modules, and building management systems requiring stable component supply across extended product lifecycles.
Supply support for R5F564MLGDFB#31 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.
The RX64M Group - including R5F564MLGDFB#31 - was designed for high-integrity industrial networking applications demanding deterministic real-time performance, multi-protocol connectivity, and built-in functional safety mechanisms.
FAQ
What is the maximum operating frequency and DMIPS rating of the R5F564MLGDFB#31?
The R5F564MLGDFB#31 operates at a maximum frequency of 120 MHz and delivers 240 DMIPS of processing performance. This is achieved through its RXv2 CPU core with 5-stage pipeline, single-cycle 32-bit multiplier, and integrated floating-point unit compliant with IEEE-754 single-precision standard - enabling efficient execution of real-time control algorithms and communication stack processing within the R5F564MLGDFB#31.
Does the R5F564MLGDFB#31 support IEEE 1588 Precision Time Protocol, and how is it implemented?
Yes, the R5F564MLGDFB#31 supports IEEE 1588 PTP via its dedicated EPTPC (Precision Time Protocol Controller) block, tightly coupled to both Ethernet MACs. It provides hardware timestamping of ingress/egress frames with sub-microsecond resolution, independent of CPU load. This implementation ensures deterministic time synchronization for distributed industrial control networks - a core capability of the R5F564MLGDFB#31 validated in Renesas' R01DS0173EJ0120 datasheet.
What are the flash and RAM capacities of the R5F564MLGDFB#31, and do they support background operation?
The R5F564MLGDFB#31 integrates 4 MB of on-chip code flash memory and 64 KB of data flash memory, both supporting Background Operation (BGO) - allowing simultaneous program execution and flash erase/write. It also includes 512 KB of general-purpose SRAM (no wait states), 32 KB of ECC-protected RAM, and 8 KB of battery-backed standby RAM. These memory resources are fully specified for the R5F564MLGDFB#31 in the RX64M Group datasheet Rev.1.20.
Which communication interfaces are included in the R5F564MLGDFB#31, and does it support dual Ethernet?
The R5F564MLGDFB#31 includes dual IEEE 802.3-compliant Ethernet MACs with MII/RMII support, three ISO 11898-1 CAN controllers, full-speed USB 2.0 with battery charging (USBA), nine SCI channels, four SCIFA interfaces, two I²C buses, QSPI, SDHI, SSI, and SRC. Dual Ethernet is confirmed for the 176-pin package variant - specifically enabled in the R5F564MLGDFB#31 per Table 1.2 of the official datasheet.
Is the R5F564MLGDFB#31 qualified for functional safety standards such as IEC60730?
Yes, the R5F564MLGDFB#31 includes hardware features certified for IEC60730 Class B compliance: oscillation-stop detection, hardware CRC generator, windowed independent watchdog timer (IWDTa), A/D converter self-diagnostic function, and register write protection. These capabilities are documented in the R5F564MLGDFB#31 datasheet section "Useful functions for IEC60730 compliance" and form part of its safety-oriented design rationale.
R5F564MLGDFB#31 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 144-LQFP
- Series:
- RX600
- Packaging:
- Tray
- Product Status:
- Discontinued at Digi-Key
- Programmable:
- Not Verified
- Core Processor:
- RXv2
- Core Size:
- 32-Bit Single-Core
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, SCI, SPI, SSI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 111
- Program Memory Size:
- 4MB (4M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 64K x 8
- RAM Size:
- 552K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 29x12b; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F564MLGDFB#31 FAQ
1.How can I place an order for R5F564MLGDFB#31 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F564MLGDFB#31 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F564MLGDFB#31 reliable?
The price and inventory of R5F564MLGDFB#31 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F564MLGDFB#31 is usually 5 days.
3.What payment methods are accepted for R5F564MLGDFB#31?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F564MLGDFB#31 transactions.
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4.How is shipping managed for R5F564MLGDFB#31?
R5F564MLGDFB#31 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F564MLGDFB#31 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F564MLGDFB#31?
For technical support, including R5F564MLGDFB#31 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F564MLGDFB#31 requirements.
6.How does Aetrix verify that R5F564MLGDFB#31 is sourced from the original manufacturer or authorized distributors?
All R5F564MLGDFB#31 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F564MLGDFB#31 meets industry standards.
7.What is the process for return or replacement of R5F564MLGDFB#31?
All R5F564MLGDFB#31 units undergo pre-shipment inspection (PSI). If there is an issue with R5F564MLGDFB#31, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F564MLGDFB#31 part is unused and in its original packaging.
Return procedure for R5F564MLGDFB#31:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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