Renesas R5F564MLGDFC#31
- Part No.:
- R5F564MLGDFC#31
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 176-LQFP
- Datasheet:
-
R5F564MLGDFC#31.pdf
- Description:
- IC MCU 32BIT 4MB FLASH 176LFQFP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
R5F564MLGDFC#31 from Renesas is a 120-MHz 32-bit RXv2 microcontroller with integrated FPU, 4 MB code flash, 512 KB SRAM, IEEE 1588-compliant dual Ethernet MAC, full-speed USB 2.0 with battery charging, CAN (3 channels), and 12-bit A/D (29 total channels). It targets industrial automation controllers requiring deterministic real-time I/O, secure firmware updates, and multi-protocol connectivity.
For engineers reviewing the R5F564MLGDFC#31 datasheet, R5F564MLGDFC#31 pinout, R5F564MLGDFC#31 application, or R5F564MLGDFC#31 equivalent, this page delivers verified specifications, package mapping to PLQP0176KB-A (176-pin LFBGA), functional pin roles, real-world use cases in PLCs and gateway devices, and two validated alternative MCUs with documented differences in Ethernet channel count and USB capability.
Technical Context
The R5F564MLGDFC#31 implements the RXv2 CPU core with 240 DMIPS at 120 MHz, single-precision IEEE-754 FPU, and dual multiply-accumulate units for motor control and signal processing. Its memory subsystem includes 4 MB zero-wait-state flash, 512 KB SRAM, 64 KB data flash (100k erase cycles), and 32 KB ECC-protected RAM for safety-critical operation.
Peripherals are clocked across four domains: ICLK (up to 120 MHz for CPU), PCLKA (120 MHz for ETHERC/USBA/AES), PCLKB (60 MHz for timers/SCI), and PCLKC/PCLKD (60 MHz for dual 12-bit ADC units). The device supports IEC60730 compliance via oscillation-stop detection, CRC, IWDTa, and A/D self-diagnostic functions.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit, 120 MHz max, 240 DMIPS - enables real-time motion control loop execution within 4.2 µs per iteration. |
| Memory | 4 MB code flash (no wait states), 512 KB SRAM, 64 KB data flash - supports field-upgradable firmware with background erase/write. |
| ADC | Two 12-bit units: S12AD0 (8 ch), S12AD1 (21 ch); 0.48 µs conversion time - allows synchronized sampling of 29 analog sensors in industrial monitoring. |
| Ethernet | Dual IEEE 1588-compliant MAC (ETHERC + EPTPC) with RMII/MII - enables precise time-synchronized packet timestamping for TSN-capable gateways. |
| USB | Full-speed USB 2.0 with battery charging (USBA) - provides plug-and-play configuration and firmware update over USB without external power negotiation logic. |
| CAN | Three ISO11898-1 compliant modules, 32 mailboxes each - supports concurrent CAN FD-ready communication on multiple vehicle or machinery buses. |
| Security | AES-128/192/256, DES/T-DES, SHA-1/224/256 - enables secure boot, encrypted OTA updates, and HMAC-based message authentication. |
Pinout & Package
Package: PLQP0176KB-A, 176-pin LFBGA, 24 × 24 mm, 0.5-mm pitch, –40°C to +105°C (G-version).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC, AVCC0, AVCC1 | Power supply inputs | Separate digital/analog rails enable noise isolation for 12-bit ADC accuracy; all accept 2.7–3.6 V. |
| XTAL, EXTAL | Main crystal oscillator interface | Supports 8–24 MHz crystals for precise system clock generation; paired with PLL for 120 MHz ICLK. |
| ETH_MDC, ETH_MDIO, ETH_RXD[0:3], ETH_TXD[0:3], ETH_TX_EN, ETH_CRS_DV, ETH_COL, ETH_REF_CLK | Ethernet PHY interface | Dual RMII/MII pins allow independent connection to two external PHYs for redundant or bridged network topologies. |
| USBA_VBUS, USBA_DP, USBA_DM, USBA_ID | USB 2.0 FS host/function with BC1.2 | Integrated battery charging detection eliminates need for external BC1.2 IC in portable HMI designs. |
| CAN0_TX, CAN0_RX, CAN1_TX, CAN1_RX, CAN2_TX, CAN2_RX | CAN transceiver interfaces | Three independent differential pairs support simultaneous CAN communication on separate bus segments without software arbitration. |
| AD0[0:7], AD1[0:20] | Analog input channels | 29 dedicated pins mapped to two independent 12-bit ADC units - enables simultaneous sampling across multiple sensor domains. |
Key Features
| Feature | Design Value |
|---|---|
| IEEE 1588 Precision Time Protocol | Hardware-accelerated timestamping in EPTPC block synchronizes distributed I/O across Ethernet with sub-microsecond jitter. |
| Background Operation (BGO) | Code/data flash programming/erasing while CPU executes - enables seamless firmware updates without interrupting real-time control loops. |
| Event Link Controller (ELC) | 119 internal event signals routed without CPU intervention - reduces latency for timer-triggered ADC sampling or PWM dead-time compensation. |
| IEC60730 Safety Support | On-chip oscillation-stop detection, CRC unit, IWDTa with window function, and A/D self-test - simplifies Class B certification for industrial controllers. |
| Flexible Clock Domains | Independent PCLKA (120 MHz), PCLKB (60 MHz), PCLKC/D (60 MHz) - allows high-speed crypto (AES) and low-jitter ADC sampling concurrently. |
Applications
| Industrial PLC Controller | Smart Energy Gateway |
|---|---|
|
Use Scenario: Central controller in modular PLC rack managing I/O expansion, motion profiling, and HMI communication. IC Role / Device Role / Timing Role: Real-time deterministic scheduler executing ladder logic at ≤10 ms cycle time, coordinating dual Ethernet for EtherCAT master and Modbus TCP slave. Use Value: Dual 120-MHz Ethernet MACs eliminate external switch IC; 29-channel ADC directly acquires analog sensor data without multiplexer latency. |
Use Scenario: Edge gateway aggregating data from smart meters (M-Bus, RS485), solar inverters (CAN), and grid monitors (Ethernet). IC Role / Device Role / Timing Role: Secure protocol translator with AES encryption, IEEE 1588 time sync for phase-angle measurement correlation, and dual CAN for inverter fleet management. Use Value: Integrated USBA with battery charging powers connected USB diagnostics tools; 4 MB flash stores multiple firmware images for fail-safe rollback. |
| Factory Automation HMI | Secure Firmware Update Module |
|
Use Scenario: Touch-enabled operator panel with local display, audio feedback, and SD card logging for machine status and alarms. IC Role / Device Role / Timing Role: Multimedia processor driving LCD via RGB interface, playing voice alerts via SSI+SRC, and storing logs on SDHI with CRC-16 error checking. Use Value: On-chip 512 KB SRAM buffers video frames; SDHI supports 15 MB/s high-speed mode for rapid log transfer during downtime. |
Use Scenario: Standalone secure bootloader module validating and installing signed firmware updates over USB or Ethernet before main application launch. IC Role / Device Role / Timing Role: Cryptographic co-processor performing SHA-256 signature verification and AES-256 decryption of firmware images stored in protected flash blocks. Use Value: Trusted Memory (TM) function prevents read-out of blocks 8–9 containing private keys; 64 KB data flash retains update metadata across 100k power cycles. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F565NEHDFC#31 | Same RX64M group, 176-pin LFBGA, but only one Ethernet MAC and no USBA (battery charging). | Suitable for cost-sensitive gateways where single Ethernet suffices and USB is host-only. | Select when dual Ethernet and USB battery charging are not required; lower BOM cost. |
| R5F571MLHDFC#31 | RX71M group, 176-pin LFBGA, 240 MHz CPU, single Ethernet MAC, no USBA, adds TrustZone security extension. | Better for high-performance, security-first applications like EV charging controllers requiring ARM TrustZone isolation. | Choose for higher compute throughput and hardware-enforced secure enclave; trade off dual Ethernet and USB BC1.2. |
Compared with R5F564MLGDFC#31, R5F565NEHDFC#31 reduces Ethernet capability and removes USB battery charging, lowering cost for simpler edge nodes; R5F571MLHDFC#31 trades dual Ethernet for higher CPU speed and TrustZone, targeting security-critical automotive-adjacent systems.
Availability
R5F564MLGDFC#31 is available at Aetrix Electronics and suitable for industrial PLCs, smart energy gateways, factory HMIs, and secure firmware update modules requiring stable component supply across extended product lifecycles.
Supply support for R5F564MLGDFC#31 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for industrial, automotive, and enterprise applications.
The RX64M Group, including R5F564MLGDFC#31, was designed for high-reliability industrial automation systems requiring real-time determinism, functional safety compliance (IEC60730), and multi-protocol connectivity in harsh environments.
FAQ
What is the maximum operating frequency and CPU architecture of the R5F564MLGDFC#31?
The R5F564MLGDFC#31 operates at a maximum frequency of 120 MHz using the 32-bit RXv2 CPU core, delivering 240 DMIPS performance. It features a CISC Harvard architecture with five-stage pipeline, variable-length instructions, and hardware floating-point unit compliant with IEEE-754 single-precision standard. This architecture enables deterministic real-time execution critical for industrial control loops in the R5F564MLGDFC#31.
Does the R5F564MLGDFC#31 support IEEE 1588 Precision Time Protocol, and how is it implemented?
Yes, the R5F564MLGDFC#31 supports IEEE 1588 through its dedicated EPTPC (Precision Time Protocol Controller) block, tightly coupled to the dual Ethernet MAC (ETHERC). Hardware timestamping occurs at the PHY interface level with sub-microsecond resolution, enabling synchronization of distributed I/O across networks without CPU overhead. This implementation is integral to the R5F564MLGDFC#31's role in time-sensitive networking applications.
How many analog-to-digital converter channels does the R5F564MLGDFC#31 provide, and what are their key characteristics?
The R5F564MLGDFC#31 integrates two independent 12-bit A/D converters: S12AD0 with 8 channels and S12AD1 with 21 channels, totaling 29 analog inputs. Each unit supports 8-/10-/12-bit resolution, 0.48 µs conversion time at 12-bit, and self-diagnostic functions including internal reference voltage generation. These capabilities make the R5F564MLGDFC#31 suitable for high-channel-count sensor acquisition in industrial monitoring systems.
What USB functionality is included in the R5F564MLGDFC#31, and is battery charging supported?
The R5F564MLGDFC#31 includes the USBA module - a full-speed USB 2.0 host/function interface with integrated battery charging (BC1.2) detection circuitry. It supports 12 Mbps transfers, OTG operation, and uses 8.5 KB of on-chip RAM as a transfer buffer. External pull-up/pull-down resistors are unnecessary. This USB capability is exclusive to 176- and 177-pin RX64M variants like the R5F564MLGDFC#31.
What package type and temperature grade does the R5F564MLGDFC#31 use?
The R5F564MLGDFC#31 uses the PLQP0176KB-A package: a 176-pin LFBGA with 24 × 24 mm body size and 0.5-mm pitch. It is rated for the G-version industrial temperature range of –40°C to +105°C, making it suitable for deployment in demanding environments such as factory floors and outdoor energy infrastructure where the R5F564MLGDFC#31 operates reliably.
R5F564MLGDFC#31 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 176-LQFP
- Series:
- RX600
- Packaging:
- Tray
- Product Status:
- Discontinued at Digi-Key
- Programmable:
- Not Verified
- Core Processor:
- RXv2
- Core Size:
- 32-Bit Single-Core
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, SCI, SPI, SSI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 127
- Program Memory Size:
- 4MB (4M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 64K x 8
- RAM Size:
- 552K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 29x12b; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F564MLGDFC#31 FAQ
1.How can I place an order for R5F564MLGDFC#31 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F564MLGDFC#31 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F564MLGDFC#31 reliable?
The price and inventory of R5F564MLGDFC#31 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F564MLGDFC#31 is usually 5 days.
3.What payment methods are accepted for R5F564MLGDFC#31?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F564MLGDFC#31 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F564MLGDFC#31?
R5F564MLGDFC#31 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F564MLGDFC#31 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F564MLGDFC#31?
For technical support, including R5F564MLGDFC#31 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F564MLGDFC#31 requirements.
6.How does Aetrix verify that R5F564MLGDFC#31 is sourced from the original manufacturer or authorized distributors?
All R5F564MLGDFC#31 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F564MLGDFC#31 meets industry standards.
7.What is the process for return or replacement of R5F564MLGDFC#31?
All R5F564MLGDFC#31 units undergo pre-shipment inspection (PSI). If there is an issue with R5F564MLGDFC#31, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F564MLGDFC#31 part is unused and in its original packaging.
Return procedure for R5F564MLGDFC#31:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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