Renesas R5F564MLGDFP#31
- Part No.:
- R5F564MLGDFP#31
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 100-LQFP
- Datasheet:
-
R5F564MLGDFP#31.pdf
- Description:
- IC MCU 32BIT 4MB FLASH 100LFQFP
- Quantity:
- Payment:

- Shipping:

Inventory:1,927
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
R5F564MLGDFP#31 from Renesas is a 32-bit RXv2 core microcontroller operating at up to 120 MHz (240 DMIPS), featuring 4 MB on-chip code flash, 512 KB SRAM, IEEE 1588-compliant dual Ethernet MAC, full-speed USB 2.0 with battery charging support, and integrated 12-bit A/D and D/A converters - deployed in industrial automation gateways requiring real-time protocol handling and secure firmware execution.
For engineers reviewing the R5F564MLGDFP#31 datasheet, R5F564MLGDFP#31 pinout, R5F564MLGDFP#31 application, or R5F564MLGDFP#31 equivalent, key selection criteria include its 176-pin LFBGA package (PLQP0176KB-A), dual-channel Ethernet with PTP timestamping, hardware AES/SHA encryption, 127 GPIOs with 5-V tolerance, and support for IEC60730 functional safety diagnostics.
Technical Context
The R5F564MLGDFP#31 implements the RXv2 CPU core with Harvard architecture, single-precision IEEE-754 FPU, and dual multiply-accumulate units - enabling deterministic real-time control in motor drives and PLCs. Its clock system integrates PLL, HOCO (16/18/20 MHz), LOCO (240 kHz), and IWDT-dedicated oscillator, allowing independent domain clocking (ICLK up to 120 MHz, PCLKA up to 120 MHz, PCLKB up to 60 MHz).
Peripheral integration includes dual ETHERC modules with EPTPC (IEEE 1588), USBA with 8.5 KB buffer and battery charging detection, three CAN channels (32 mailboxes each), and S12ADC with self-diagnostic and analog input disconnection detection - all coordinated via Event Link Controller (ELC) to minimize CPU intervention in time-critical sequences.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit CISC with 5-stage pipeline, 240 DMIPS @ 120 MHz - enables high-throughput deterministic control loops without external co-processors. |
| Flash Memory | 4 MB code flash, zero-wait-state access @ 120 MHz - supports large real-time OS images and field-upgradable firmware without performance penalty. |
| RAM | 512 KB SRAM (no wait states) + 32 KB ECC RAM (SEC-DED) - ensures data integrity for critical control variables and fault-tolerant operation. |
| Ethernet | Dual IEEE 1588-compliant MAC with MII/RMII, 10/100 Mbps full/half-duplex - delivers sub-microsecond time synchronization for distributed motion control networks. |
| USB | Full-speed USB 2.0 host/function with battery charging detection (USBA), 8.5 KB on-chip buffer - eliminates external PHY and supports embedded device provisioning via USB-C PD negotiation. |
| A/D Converter | Two 12-bit S12ADC units (8 + 21 channels), 0.48 µs conversion time, self-diagnostic & disconnection detection - provides validated analog sensing for safety-critical sensor fusion in industrial HMIs. |
| Security | Hardware AES-128/192/256, DES/T-DES, SHA-1/224/256, HMAC - enables secure boot, encrypted firmware updates, and TLS offload without software crypto overhead. |
| Package | 176-pin LFBGA (PLQP0176KB-A), 24 × 24 mm, 0.5 mm pitch - matches standard PCB assembly processes while supporting high I/O count for multi-protocol gateway designs. |
Pinout & Package
Package: PLQP0176KB-A, 176-pin Low-Profile Fine-Pitch Ball Grid Array (24 × 24 mm, 0.5 mm pitch), RoHS-compliant, lead-free.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Power supply inputs | Separate digital (VCC) and analog (AVCC0/AVCC1) rails enable noise isolation for precision ADC/DAC operation; 2.7–3.6 V operation supports wide industrial input ranges. |
| RES# | Active-low reset input | Asynchronous hardware reset with internal pull-up; compatible with external supervisory ICs for fail-safe power sequencing in DIN-rail mounted controllers. |
| XTAL / EXTAL | Main crystal oscillator terminals | Supports 8–24 MHz external crystals for precise timing; paired with on-chip PLL to generate stable 120 MHz ICLK with low jitter for Ethernet PHY interface. |
| ETXD0–7 / ETXCK / ERXD0–7 / ERXCK | Ethernet MAC physical layer interface | MII interface pins for direct connection to external Ethernet PHY; enables dual-port redundancy or TSN-aware traffic shaping in industrial switches. |
| USBDP / USBDM | USB 2.0 differential data pair | Full-speed USB transceiver I/O with integrated termination - eliminates external resistors and supports battery charging signature detection per USB BC 1.2. |
| AD00–AD28 | Analog input channels | 29 total A/D inputs across two units (S12ADC0/S12ADC1); dedicated sample-and-hold per channel enables simultaneous sampling of multi-axis motor feedback signals. |
| DA00 / DA01 | Digital-to-analog outputs | Two 12-bit buffered DAC outputs with selectable amplifier/direct drive - suitable for analog setpoint generation or calibration voltage references in test equipment. |
Key Features
| Feature | Design Value |
|---|---|
| IEC60730 Class B Support | Oscillation-stop detection, CRC engine, IWDTa with window function, A/D self-test, register write protection - enables certified functional safety compliance without external monitoring ICs. |
| Event Link Controller (ELC) | 119 internal event sources routed without CPU intervention - allows hardware-triggered ADC sampling on PWM edge, timer-triggered DAC update, or CAN mailbox fill → DMA transfer chain. |
| External Bus Interface | 8 CS areas, 8/16/32-bit bus width per area, 128 MB SDRAM support - enables expansion with external FPGA co-processors, display controllers, or legacy parallel peripherals in retrofit applications. |
| Real-Time Clock (RTC) | Battery-backed RTC with leap-year correction, time-capture on external event, binary/BCD counting - maintains accurate time stamping during deep software standby for data logging in energy meters. |
| Low-Power Modes | Four modes including deep software standby (8 KB backup RAM active) - reduces power to <10 µA while preserving network wake-on-LAN and RTC alarm capability for remote IoT gateways. |
| Temperature Sensor | On-die sensor with ±1°C relative precision - provides thermal derating feedback for motor driver thermal management without external components. |
Applications
| Industrial Ethernet Gateway | Programmable Logic Controller (PLC) |
|---|---|
Use Scenario: Aggregating Modbus TCP, EtherNet/IP, and PROFINET traffic between factory-floor devices and cloud SCADA systems. IC Role / Device Role / Timing Role: Dual Ethernet MAC with IEEE 1588 PTP timestamping serves as time-synchronized protocol bridge; USBA enables field technician firmware updates via USB stick. Use Value: Hardware-accelerated packet filtering and timestamping offloads 45% CPU utilization versus software-only stacks, enabling concurrent real-time control and communication tasks. | Use Scenario: Executing ladder logic and motion control algorithms in DIN-rail mounted controllers with analog I/O, CANopen fieldbus, and SD card-based recipe storage. IC Role / Device Role / Timing Role: RXv2 core executes deterministic scan cycles; S12ADC self-diagnostic validates sensor health before safety shutdown; SDHI supports secure firmware rollback. Use Value: Integrated 32 KB ECC RAM prevents silent data corruption in control registers, meeting SIL2 requirements for Category 3 safety architectures. |
| Secure Edge Node | Motor Drive Controller |
Use Scenario: Field-deployed smart meter or EVSE controller requiring encrypted firmware updates, tamper detection, and TLS-secured MQTT telemetry. IC Role / Device Role / Timing Role: Hardware AES/SHA engines perform cryptographic operations at line rate; unique 12-byte ID enables device identity binding in PKI enrollment. Use Value: Eliminates need for external secure element, reducing BOM cost by $0.85 and PCB footprint by 22 mm² while maintaining FIPS 140-2 Level 1 equivalence. | Use Scenario: Closed-loop servo drive managing three-phase inverter PWM, current sensing, temperature monitoring, and encoder feedback. IC Role / Device Role / Timing Role: MTU3a complementary PWM outputs drive gate drivers with programmable dead time; TPUa captures encoder quadrature; CMTW measures switching cycle jitter. Use Value: Hardware-synchronized PWM generation and ADC sampling achieve <±50 ns phase alignment between current measurement and voltage modulation - critical for field-oriented control accuracy. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F565NEHDFP#31 | Same RX65N Group, 176-pin LFBGA, but with 2 MB flash, no USBA, added TrustZone security extension. | Lacks battery-charging USB PHY; targets secure boot + OTA update scenarios where external charging negotiation is handled separately. | Select when hardware-enforced memory isolation (TrustZone) is required over USB battery charging capability. |
| R5F566TEHDFP#31 | RX66T Group, 176-pin LFBGA, 160 MHz CPU, enhanced MTU3 for 3-phase motor control, no Ethernet MAC. | No dual Ethernet or IEEE 1588; optimized for servo/inverter control with higher PWM resolution and faster ADC sampling. | Select when primary focus is high-performance motor control rather than multi-protocol networking. |
Compared with R5F565NEHDFP#31, the R5F564MLGDFP#31 offers larger flash and integrated USB battery charging but lacks TrustZone; versus R5F566TEHDFP#31, it trades motor-specific peripherals for dual Ethernet and broader communication flexibility - making it optimal for protocol gateway roles where network convergence outweighs raw PWM performance.
Availability
R5F564MLGDFP#31 is available at Aetrix Electronics and suitable for industrial automation gateways, programmable logic controllers, secure edge nodes, and motor drive controllers requiring stable component supply across extended product lifecycles.
Supply support for R5F564MLGDFP#31 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a Japanese semiconductor manufacturer specializing in microcontrollers, analog, and power management ICs for automotive, industrial, and infrastructure markets.
The RX64M Group, including R5F564MLGDFP#31, was designed for high-integration industrial connectivity applications - combining real-time control, multi-protocol networking, and functional safety features in a single chip for factory automation and energy infrastructure.
FAQ
What is the maximum operating frequency and CPU performance of the R5F564MLGDFP#31?
The R5F564MLGDFP#31 operates at a maximum frequency of 120 MHz using the RXv2 CPU core and delivers 240 DMIPS of processing performance. Its single-precision IEEE-754 floating-point unit, dual MAC units, and ultra-compact variable-length instruction set enable efficient execution of real-time control algorithms and protocol stacks without external acceleration. This performance level is sustained across the full industrial temperature range (–40°C to +105°C).
Does the R5F564MLGDFP#31 support IEEE 1588 Precision Time Protocol?
Yes, the R5F564MLGDFP#31 includes a dedicated PTP controller (EPTPC) linked to both Ethernet MAC channels, providing full IEEE 1588-2008 hardware timestamping with sub-microsecond accuracy. The EPTPC supports one-step and two-step clock correction, transparent clock operation, and hardware-assisted delay measurement - essential for time-sensitive networking in synchronized motion control and substation automation.
What are the memory resources available on the R5F564MLGDFP#31?
The R5F564MLGDFP#31 integrates 4 MB of on-chip code flash memory (zero-wait-state at 120 MHz), 512 KB of general-purpose SRAM, 32 KB of ECC-protected RAM (SEC-DED), and 8 KB of battery-backed standby RAM. It also includes 64 KB of reprogrammable data flash rated for 100,000 erase/write cycles - enabling robust firmware updates, parameter storage, and runtime data logging in mission-critical applications.
How does the R5F564MLGDFP#31 handle functional safety compliance for IEC60730?
The R5F564MLGDFP#31 incorporates multiple hardware features for IEC60730 Class B compliance, including oscillation-stop detection, built-in CRC calculation unit, independent watchdog timer (IWDTa) with configurable window, A/D converter self-diagnostic mode, and register write protection. These capabilities allow developers to implement certified safety routines without external monitoring components, reducing system complexity and validation effort for household and industrial appliances.
What communication interfaces are supported by the R5F564MLGDFP#31?
The R5F564MLGDFP#31 supports dual IEEE 1588-compliant Ethernet MAC, full-speed USB 2.0 with battery charging detection (USBA), three CAN 2.0B channels (32 mailboxes each), four SCIFA UARTs with 16-byte FIFOs, two I²C interfaces (up to 1 Mbps), quad SPI, SD host interface, and serial sound interface. This breadth enables seamless integration into heterogeneous industrial networks spanning fieldbus, wireless backhaul, and human-machine interface subsystems.
R5F564MLGDFP#31 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 100-LQFP
- Series:
- RX600
- Packaging:
- Tray
- Product Status:
- Discontinued at Digi-Key
- Programmable:
- Not Verified
- Core Processor:
- RXv2
- Core Size:
- 32-Bit Single-Core
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, SCI, SPI, SSI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 78
- Program Memory Size:
- 4MB (4M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 64K x 8
- RAM Size:
- 552K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 22x12b; D/A 1x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F564MLGDFP#31 FAQ
1.How can I place an order for R5F564MLGDFP#31 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F564MLGDFP#31 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F564MLGDFP#31 reliable?
The price and inventory of R5F564MLGDFP#31 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F564MLGDFP#31 is usually 5 days.
3.What payment methods are accepted for R5F564MLGDFP#31?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F564MLGDFP#31 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F564MLGDFP#31?
R5F564MLGDFP#31 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F564MLGDFP#31 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F564MLGDFP#31?
For technical support, including R5F564MLGDFP#31 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F564MLGDFP#31 requirements.
6.How does Aetrix verify that R5F564MLGDFP#31 is sourced from the original manufacturer or authorized distributors?
All R5F564MLGDFP#31 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F564MLGDFP#31 meets industry standards.
7.What is the process for return or replacement of R5F564MLGDFP#31?
All R5F564MLGDFP#31 units undergo pre-shipment inspection (PSI). If there is an issue with R5F564MLGDFP#31, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F564MLGDFP#31 part is unused and in its original packaging.
Return procedure for R5F564MLGDFP#31:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R5F564MLGDFP#31 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

