Renesas R5F564MLGDLC#21
- Part No.:
- R5F564MLGDLC#21
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 177-TFLGA
- Datasheet:
-
R5F564MLGDLC#21.pdf
- Description:
- IC MCU 32BIT 4MB FLASH 177TFLGA
- Quantity:
- Payment:

- Shipping:

Inventory:319
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
R5F564MLGDLC#21 from Renesas is a 120-MHz 32-bit RXv2 microcontroller with single-precision IEEE-754 FPU, 4 MB on-chip code flash, 512 KB SRAM, and integrated IEEE 1588-compliant Ethernet MAC - designed for industrial automation gateways requiring deterministic real-time control, secure connectivity, and high-integration embedded processing.
For engineers reviewing the R5F564MLGDLC#21 datasheet, R5F564MLGDLC#21 pinout, R5F564MLGDLC#21 application, or R5F564MLGDLC#21 equivalent, this MCU delivers verified 240 DMIPS performance, dual 12-bit ADCs (29 total channels), full-speed USB 2.0 with battery charging support, CAN FD-capable interfaces, and hardware-accelerated AES/SHA encryption - all in a 176-pin LFBGA package rated for –40°C to +105°C operation.
Technical Context
The R5F564MLGDLC#21 implements the RXv2 CPU core with CISC Harvard architecture, 5-stage pipeline, and variable-length instructions enabling ultra-compact code density. It integrates dual clock domains: ICLK up to 120 MHz for CPU and high-speed peripherals (ETHERC, USBA, AES), and PCLKB up to 60 MHz for timers, ADCs, and communication modules.
Its peripheral subsystem includes three independent CAN modules (ISO 11898-1 compliant, 32 mailboxes each), two IEEE 1588 PTP-enabled Ethernet controllers with RMII/MII support, and a dedicated SD host interface (SDHI) compliant with SD Physical Layer Spec v3.01 - all coordinated via the Event Link Controller (ELC) for zero-CPU-intervention signal chaining.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit CISC core with 5-stage pipeline, 240 DMIPS @ 120 MHz, IEEE-754 single-precision FPU |
| Memory | 4 MB code flash (no wait states @ 120 MHz), 64 KB data flash (100k erase cycles), 512 KB SRAM (no wait), 32 KB ECC RAM |
| Operating Voltage | 2.7 V to 3.6 V supply; supports RTC backup via VBATT pin during main power loss |
| Temperature Range | –40°C to +105°C (G-version), qualified for industrial and extended-temperature embedded systems |
| Communication | Dual IEEE 1588 Ethernet MAC (RMII/MII), 3× CAN, 9× SCI, 4× SCIFA, 2× RIIC, QSPI, SDHI, USB 2.0 FS with battery charging |
| Analog Peripherals | Two 12-bit ADC units (8 + 21 channels), 2× 12-bit DAC, on-chip temperature sensor (±1°C), self-diagnostic A/D functionality |
| Security | Optional hardware AES (128/192/256), DES/T-DES, SHA-1/SHA-224/SHA-256, HMAC, and trusted memory (TM) protection for flash blocks 8–9 |
Pinout & Package
Package: PLQP0176KB-A - 176-pin LFBGA, 24 mm × 24 mm, 0.5 mm pitch, RoHS-compliant, moisture sensitivity level 3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Main and analog power supply pins | Separate analog/digital domains enable noise isolation; AVCC1 powers S12AD unit 1 and R12DA |
| VBATT | Battery backup supply | Enables RTC operation during main power failure; requires external coin-cell or supercapacitor |
| RES# | Active-low reset input | Hardware reset assertion; internal pull-up ensures reliable startup without external resistor |
| EXCLK / EXTAL / XTAL | External clock inputs | Supports 8–24 MHz crystal/resonator for main clock; sub-clock input for RTC precision timing |
| ETXD0–7 / ETXCK / ERXD0–7 / ERXCK | Ethernet PHY interface signals | Direct RMII/MII connection to external PHY; no external transceiver required for basic 10/100 Mbps operation |
| USBDP / USBDM | USB 2.0 full-speed differential pair | Integrated transceiver eliminates need for external USB PHY; supports host/function/OTG modes |
| TXD0 / RXD0 | SCI0 asynchronous serial interface | Primary debug and bootloader interface; 16-byte FIFO enables robust UART-based firmware updates |
Key Features
| Feature | Design Value |
|---|---|
| IEEE 1588 Precision Time Protocol | Hardware timestamping engine synchronized to Ethernet frames enables sub-microsecond time synchronization for industrial PLCs and motion controllers |
| Event Link Controller (ELC) | 119 internal event sources can trigger timer starts, ADC conversions, or GPIO toggles without CPU intervention - reducing latency and jitter in real-time loops |
| Background Operation (BGO) | Simultaneous code flash programming/erasing while executing application code - essential for field-upgradable firmware in deployed equipment |
| IEC 60730 Safety Support | Integrated oscillation-stop detection, CRC calculation unit, IWDT windowing, and A/D self-diagnostic meet Class B functional safety requirements |
| Flexible Clock Architecture | Independent PLL, HOCO (16/18/20 MHz), LOCO (240 kHz), and IWDT-dedicated oscillator allow dynamic clock scaling and fail-safe fallback modes |
Applications
| Industrial Ethernet Gateway | Smart Energy Metering Hub |
|---|---|
Use Scenario: Aggregating Modbus TCP, CANopen, and BACnet MS/TP traffic across factory-floor devices into unified OPC UA over Ethernet. IC Role / Device Role / Timing Role: Primary application processor with dual Ethernet MACs handling protocol translation, real-time scheduling, and secure TLS tunneling. Use Value: IEEE 1588 PTP hardware timestamping ensures synchronized sampling of distributed I/O across multiple network segments within ±250 ns. | Use Scenario: Multi-tariff electricity meter with tamper detection, remote firmware update, and grid-edge analytics using edge AI inference. IC Role / Device Role / Timing Role: System-on-chip controller managing metrology ADCs, secure key storage, SD card logging, and cellular backhaul via USB or UART. Use Value: On-chip AES-256 and SHA-256 accelerate DLMS/COSEM security stack execution while preserving 120 MHz CPU bandwidth for real-time FFT analysis. |
| Programmable Logic Controller (PLC) | Automotive Diagnostic Tool |
Use Scenario: Compact DIN-rail PLC with 16 digital I/O, 4 analog inputs, and EtherCAT slave capability for machine control. IC Role / Device Role / Timing Role: Real-time deterministic controller running IEC 61131-3 logic with cycle times under 1 ms, leveraging MTU3 PWM and ELC-triggered ADC sampling. Use Value: Complementary PWM outputs with programmable dead-time generation directly drive 3-phase motor inverters without external gate drivers. | Use Scenario: Handheld OBD-II scanner supporting UDS, DoIP, and J1939 diagnostics over CAN, USB, and Wi-Fi (via external module). IC Role / Device Role / Timing Role: Host MCU interfacing with automotive networks via three independent CAN controllers and providing USB CDC/ACM virtual COM port to PC. Use Value: 32-mailbox CAN buffers per channel prevent message loss during high-bandwidth diagnostic sessions (e.g., live parameter streaming at 500 kbps). |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F565NEHDFP#30 | Same RX65N Group; 100-pin LQFP, 2 MB flash, no Ethernet MAC, adds TrustZone-based secure boot | Better suited for cost-sensitive, space-constrained designs where Ethernet is offloaded to external PHY+switch | Select when footprint, BOM cost, and secure boot outweigh need for integrated Ethernet MAC |
| R7FA6M2AF3CFP#AA0 | RX72M Group; 120 MHz, 1 MB flash, single Ethernet MAC, enhanced GPTA with 3-phase PWM, no SDHI | Optimized for servo drives and motor control with higher-resolution PWM and encoder interface support | Select when motor control precision and lower flash density are prioritized over dual Ethernet and SD card support |
Compared with R5F565NEHDFP#30 and R7FA6M2AF3CFP#AA0, the R5F564MLGDLC#21 uniquely combines dual IEEE 1588 Ethernet, 4 MB flash, SDHI, and full-speed USB with battery charging - making it the only RX-series option for compact, feature-rich industrial gateways requiring local storage, wired/wireless coexistence, and precise time-synchronized networking.
Availability
R5F564MLGDLC#21 is available at Aetrix Electronics and suitable for industrial automation gateways, smart energy meters, programmable logic controllers, and automotive diagnostic tools requiring stable component supply across multi-year production cycles.
Supply support for R5F564MLGDLC#21 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader delivering microcontrollers, analog, power, and SoC solutions for automotive, industrial, infrastructure, and IoT markets.
The RX64M Group - including R5F564MLGDLC#21 - was engineered specifically for high-performance industrial connectivity applications demanding real-time determinism, functional safety compliance (IEC 60730), and integrated secure networking.
FAQ
What is the maximum operating frequency and DMIPS rating of the R5F564MLGDLC#21?
The R5F564MLGDLC#21 operates at a maximum frequency of 120 MHz and delivers 240 DMIPS performance. This is achieved by the RXv2 CPU core's 5-stage pipeline, single-cycle 32-bit multiply, and efficient instruction set - confirmed in Renesas datasheet R01DS0173EJ0120. The R5F564MLGDLC#21 sustains this throughput across its full voltage range (2.7–3.6 V) and temperature range (–40°C to +105°C).
Does the R5F564MLGDLC#21 include hardware support for IEEE 1588 Precision Time Protocol?
Yes, the R5F564MLGDLC#21 integrates a dedicated PTP controller (EPTPC) linked to both Ethernet MACs, enabling hardware timestamping of ingress/egress Ethernet frames with sub-microsecond resolution. This allows deterministic time synchronization in industrial automation networks - a core capability documented in Section 1.1 and Table 1.1 of the R01DS0173EJ0120 datasheet for the R5F564MLGDLC#21.
How many CAN interfaces does the R5F564MLGDLC#21 support, and what is the mailbox capacity per channel?
The R5F564MLGDLC#21 supports three independent CAN modules compliant with ISO 11898-1, each with 32 dedicated mailboxes for standard and extended frame handling. This configuration is explicitly specified in the "Communication function" section (page 7) of the R01DS0173EJ0120 datasheet and applies to all 176/177-pin RX64M variants including the R5F564MLGDLC#21.
What are the flash and SRAM capacities of the R5F564MLGDLC#21?
The R5F564MLGDLC#21 includes 4 MB of on-chip code flash memory (accessible at 120 MHz with zero wait states), 64 KB of reprogrammable data flash (rated for 100,000 erase cycles), 512 KB of general-purpose SRAM (zero wait state), and 32 KB of ECC-protected RAM. These values are confirmed in Table 1.1 (pages 2–3) of the official R01DS0173EJ0120 datasheet for the R5F564MLGDLC#21.
Is the R5F564MLGDLC#21 qualified for extended temperature operation?
Yes, the R5F564MLGDLC#21 is the G-version device, rated for operation from –40°C to +105°C. This qualification is defined in the "Operating temp. range" section of the datasheet and applies specifically to part numbers ending in "G", including R5F564MLGDLC#21 - making it suitable for under-hood automotive diagnostics tools and industrial control cabinets without forced cooling.
R5F564MLGDLC#21 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 177-TFLGA
- Series:
- RX600
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- RXv2
- Core Size:
- 32-Bit Single-Core
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, SCI, SPI, SSI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 127
- Program Memory Size:
- 4MB (4M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 64K x 8
- RAM Size:
- 552K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 29x12b; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F564MLGDLC#21 FAQ
1.How can I place an order for R5F564MLGDLC#21 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F564MLGDLC#21 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F564MLGDLC#21 reliable?
The price and inventory of R5F564MLGDLC#21 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F564MLGDLC#21 is usually 5 days.
3.What payment methods are accepted for R5F564MLGDLC#21?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F564MLGDLC#21 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F564MLGDLC#21?
R5F564MLGDLC#21 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F564MLGDLC#21 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F564MLGDLC#21?
For technical support, including R5F564MLGDLC#21 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F564MLGDLC#21 requirements.
6.How does Aetrix verify that R5F564MLGDLC#21 is sourced from the original manufacturer or authorized distributors?
All R5F564MLGDLC#21 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F564MLGDLC#21 meets industry standards.
7.What is the process for return or replacement of R5F564MLGDLC#21?
All R5F564MLGDLC#21 units undergo pre-shipment inspection (PSI). If there is an issue with R5F564MLGDLC#21, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F564MLGDLC#21 part is unused and in its original packaging.
Return procedure for R5F564MLGDLC#21:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R5F564MLGDLC#21 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

