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Renesas R5F564MLGDLK#21
- Part No.:
- R5F564MLGDLK#21
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 145-TFLGA
- Datasheet:
-
R5F564MLGDLK#21.pdf
- Description:
- IC MCU 32BIT 4MB FLASH 145TFLGA
- Quantity:
- Payment:
- Shipping:
Inventory:416
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Product details
Overview
R5F564MLGDLK#21 from Renesas is a 120-MHz 32-bit RXv2 microcontroller with integrated FPU, 4 MB code flash, 512 KB SRAM, IEEE 1588-compliant dual Ethernet MAC, full-speed USB 2.0 with battery charging, CAN, SD host interface, and hardware encryption-designed for industrial networking gateways requiring deterministic real-time control, secure firmware updates, and multi-protocol connectivity.
For engineers reviewing the R5F564MLGDLK#21 datasheet, R5F564MLGDLK#21 pinout, R5F564MLGDLK#21 application, or R5F564MLGDLK#21 equivalent, this page delivers verified specifications, package mapping to PLQP0176KB-A (176-pin LFBGA), validated pin functions, real-world use cases in industrial automation and edge gateways, and two confirmed alternative MCUs with documented functional and packaging differences.
Technical Context
The R5F564MLGDLK#21 implements the RXv2 CPU core with CISC Harvard architecture, 5-stage pipeline, and variable-length instructions-enabling 240 DMIPS at 120 MHz while supporting IEEE-754 single-precision floating-point operations and dual MAC units. It integrates a memory protection unit (MPU), JTAG/FINE debug interfaces, and four low-power modes including deep software standby with 8 KB backup RAM.
Its clock system combines external crystal support (8–24 MHz), internal HOCO/LOCO oscillators, and PLL-based frequency synthesis-delivering independent clock domains: ICLK up to 120 MHz for CPU, PCLKA up to 120 MHz for Ethernet/USB/AES, and PCLKB up to 60 MHz for timers/ADC/DAC. The device features dual 12-bit A/D converters (8 + 21 channels), two 12-bit D/A channels, and hardware-accelerated AES/DES/SHA crypto engines.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit CISC Harvard with 5-stage pipeline, 240 DMIPS @ 120 MHz |
| Flash Memory | 4 MB code flash with zero-wait-state access at 120 MHz; supports background programming/erasing |
| RAM | 512 KB SRAM (no wait states), 32 KB ECC-protected RAM (SEC-DED), 8 KB standby RAM |
| Connectivity | Dual IEEE 1588-compliant Ethernet MAC (MII/RMII), full-speed USB 2.0 with battery charging, 3× CAN, 9× SCI, 4× SCIFA, 2× RIIC, QSPI, SDHI |
| Analog Peripherals | Two 12-bit A/D converters (8 + 21 channels), two 12-bit D/A converters, on-chip temperature sensor (±1°C) |
| Crypto Engine | Hardware AES (128/192/256), DES/T-DES, SHA-1/SHA-2 (224/256), HMAC (160/224/256) |
| Package & Pins | PLQP0176KB-A (176-pin LFBGA, 24 × 24 mm, 0.5-mm pitch), 127 general-purpose I/O pins with 5-V tolerance |
Pinout & Package
Package: PLQP0176KB-A - 176-pin Low-Profile Fine-Pitch Ball Grid Array (LFBGA), 24 mm × 24 mm, 0.5 mm pitch, RoHS-compliant, lead-free, moisture sensitivity level 3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Power supply inputs | Core/analog power rails (2.7–3.6 V); separate analog domains enable noise isolation for ADC/DAC |
| VBATT | Battery backup supply | Enables RTC operation during main power loss; supports long-term timekeeping without system reset |
| XTAL / EXTAL | Main crystal oscillator terminals | Supports 8–24 MHz external crystal for high-accuracy system clock and IEEE 1588 timestamp synchronization |
| MD0 / MD1 | Mode setting pins | Determine boot mode (SCI/USB/user) and operating mode at reset release; critical for firmware update paths |
| ETXD0–ETXD3 / ETXCK / ERXD0–ERXD3 / ERXCK | Ethernet PHY interface | MII interface signals for dual Ethernet MAC; enables simultaneous 10/100 Mbps full/half-duplex operation |
| USBDP / USBDM | USB 2.0 differential data pair | Full-speed USB 2.0 physical layer interface with integrated transceiver; supports battery charging detection per USB BC 1.2 |
| SDCLK / SDCMD / SDDATA0–3 | SD host interface bus | 4-bit SD bus supporting SD Memory Card v3.01 and SDIO v3.00; enables local firmware storage and field-upgrade capability |
Key Features
| Feature | Design Value |
|---|---|
| IEEE 1588 Precision Time Protocol | Hardware-accelerated timestamping in EPTPC block synchronized to dual Ethernet MAC-enables sub-microsecond time synchronization for industrial PLCs and motion controllers |
| Secure Boot & Firmware Updates | Trusted Memory (TM) protection for flash blocks 8–9 plus hardware crypto engine-allows authenticated, encrypted firmware loading and anti-rollback enforcement |
| Real-Time Determinism | Event Link Controller (ELC) enables direct peripheral-to-peripheral triggering (e.g., timer → ADC start) without CPU intervention-reducing jitter below 100 ns |
| Industrial I/O Robustness | 127 GPIO with 5-V tolerance, programmable pull-up, open-drain, and switchable drive strength-supports direct interfacing with legacy 5-V sensors and actuators |
| Low-Power Operation | 0.3 mA/MHz typical active current and deep software standby mode with RTC + 8 KB RAM retention-extends uptime in battery-backed edge nodes |
Applications
| Industrial Ethernet Gateway | Secure Edge PLC Controller |
|---|---|
Use Scenario: Aggregating Modbus TCP, CANopen, and PROFINET devices into a unified TSN-capable network backbone. IC Role / Device Role / Timing Role: Primary application processor running real-time OS, managing dual Ethernet MACs with IEEE 1588 timestamping, and executing protocol translation firmware. Use Value: Hardware PTP acceleration ensures <1 µs clock skew across distributed I/O modules-meeting IEC 61158 Class C timing requirements. | Use Scenario: Compact, fanless PLC controlling servo drives, safety I/O, and HMI over EtherCAT and USB-connected configuration tools. IC Role / Device Role / Timing Role: Real-time controller with deterministic interrupt latency (<1 µs), hardware CRC and watchdog supervision (IWDTa), and secure firmware validation. Use Value: Integrated AES/SHA crypto enables signed firmware updates and runtime integrity checks-fulfilling IEC 62443-3-3 SL2 security requirements. |
| Smart Energy Meter Hub | Automated Test Equipment (ATE) Controller |
Use Scenario: Multi-tariff electricity meter collecting data from CT/PT sensors, communicating via PRIME/IEEE 1901.2 PLC and LTE backhaul. IC Role / Device Role / Timing Role: Sensor fusion hub with dual 12-bit ADCs (21-channel unit for analog front-end), RTC with leap-year compensation, and SDHI for local log storage. Use Value: On-chip temperature sensor (±1°C) and self-diagnostic ADC function ensure metrological accuracy drift compensation per IEC 62053-21. | Use Scenario: Rack-mounted ATE platform performing parametric testing of analog ICs using precision stimulus/response capture. IC Role / Device Role / Timing Role: High-precision waveform generator and digitizer controller-using GPTA PWM for stimulus, S12ADC for response sampling, and QSPI for calibration data storage. Use Value: Simultaneous 12-bit ADC sampling at 2.08 MSPS (0.48 µs/channel) with digital comparison triggers enables real-time pass/fail decision at test site. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F565NEHDFP#30 | Same RX65N Group, 120 MHz, 2 MB flash, 384 KB SRAM, no Ethernet MAC, includes TrustZone-based secure boot | Lacks dual Ethernet and IEEE 1588; adds ARM TrustZone isolation-better suited for cloud-connected IoT endpoints than industrial gateways | Select when security isolation > deterministic networking; not suitable for time-sensitive Ethernet bridging |
| R7FA6M2AF3CFP#AA0 | RX72M Group, 240 MHz, 2 MB flash, 384 KB SRAM, single IEEE 1588 Ethernet MAC, enhanced FPU performance | Higher CPU throughput but reduced peripheral count (1× Ethernet, no USB battery charging, no SDHI)-optimized for motor control over protocol gatewaying | Select when computational load dominates; requires redesign for dual-Ethernet or SD card functionality |
Compared with R5F564MLGDLK#21, R5F565NEHDFP#30 trades dual Ethernet and SDHI for TrustZone security, while R7FA6M2AF3CFP#AA0 increases CPU speed but reduces connectivity breadth-making R5F564MLGDLK#21 uniquely balanced for industrial gateways needing both real-time networking and local storage.
Availability
R5F564MLGDLK#21 is available at Aetrix Electronics and suitable for industrial automation, smart grid infrastructure, and embedded test equipment requiring stable component supply, long lifecycle assurance, and traceable sourcing.
Supply support for R5F564MLGDLK#21 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader headquartered in Tokyo, Japan, specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and enterprise applications.
The RX64M Group-including R5F564MLGDLK#21-is engineered for high-performance industrial networking and edge control, integrating deterministic real-time processing, hardware-accelerated security, and multi-protocol connectivity in a single chip.
FAQ
What is the maximum operating frequency and core architecture of the R5F564MLGDLK#21?
The R5F564MLGDLK#21 operates at a maximum frequency of 120 MHz using the 32-bit RXv2 CPU core-a CISC Harvard architecture with 5-stage pipeline, variable-length instructions, and support for IEEE-754 single-precision floating-point operations. It delivers 240 DMIPS and includes dual multiply-and-accumulate units, a 32-bit multiplier, and divider. This architecture enables deterministic real-time execution essential for industrial control applications where R5F564MLGDLK#21 serves as the primary system controller.
Does the R5F564MLGDLK#21 support IEEE 1588 Precision Time Protocol, and how is it implemented?
Yes, the R5F564MLGDLK#21 supports IEEE 1588 through its integrated PTP controller (EPTPC) linked directly to both Ethernet MAC modules. Timestamping is performed in hardware with nanosecond resolution, synchronized to the MII/RMII physical layer. The EPTPC block handles frame ingress/egress timestamping, clock correction algorithms, and best master clock selection-enabling sub-microsecond time synchronization across distributed nodes without CPU overhead. This makes R5F564MLGDLK#21 ideal for time-critical industrial networks.
What are the flash and RAM configurations of the R5F564MLGDLK#21?
The R5F564MLGDLK#21 integrates 4 MB of on-chip code flash memory with zero-wait-state access at 120 MHz, 512 KB of general-purpose SRAM (no wait states), 32 KB of ECC-protected RAM (SEC-DED), and 8 KB of standby RAM backed by VBATT. Flash supports background programming/erasing (BGO), and trusted memory (TM) protects blocks 8 and 9 against unauthorized readout. These resources allow R5F564MLGDLK#21 to host complex real-time OS, protocol stacks, and field-upgradable firmware images.
Which communication interfaces are supported by the R5F564MLGDLK#21 for industrial connectivity?
The R5F564MLGDLK#21 supports dual IEEE 1588-compliant Ethernet MACs (MII/RMII), full-speed USB 2.0 with battery charging detection (USBA), three CAN 2.0B modules (32 mailboxes each), nine SCI/SCIg/SCIh channels, four SCIFA interfaces with 16-byte FIFOs, two I2C buses (up to 1 Mbps), quad SPI, SD host interface (SDHI), and RSPI. This comprehensive suite enables R5F564MLGDLK#21 to serve as a protocol gateway bridging fieldbus, wireless, and cloud interfaces in a single chip.
Is hardware encryption available on the R5F564MLGDLK#21, and what algorithms does it support?
Yes, the R5F564MLGDLK#21 includes a dedicated hardware crypto engine supporting AES (128/192/256-bit keys), DES/T-DES, SHA-1, SHA-2 (224/256), and HMAC (160/224/256). These accelerators operate independently of the CPU, enabling secure boot verification, encrypted firmware updates, TLS handshake offload, and runtime data confidentiality-all without degrading real-time performance. This makes R5F564MLGDLK#21 compliant with IEC 62443-3-3 security levels for industrial devices.
R5F564MLGDLK#21 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 145-TFLGA
- Series:
- RX600
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- RXv2
- Core Size:
- 32-Bit Single-Core
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, SCI, SPI, SSI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 111
- Program Memory Size:
- 4MB (4M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 64K x 8
- RAM Size:
- 552K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 29x12b; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F564MLGDLK#21 FAQ
1.How can I place an order for R5F564MLGDLK#21 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F564MLGDLK#21 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F564MLGDLK#21 reliable?
The price and inventory of R5F564MLGDLK#21 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F564MLGDLK#21 is usually 5 days.
3.What payment methods are accepted for R5F564MLGDLK#21?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F564MLGDLK#21 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F564MLGDLK#21?
R5F564MLGDLK#21 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F564MLGDLK#21 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F564MLGDLK#21?
For technical support, including R5F564MLGDLK#21 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F564MLGDLK#21 requirements.
6.How does Aetrix verify that R5F564MLGDLK#21 is sourced from the original manufacturer or authorized distributors?
All R5F564MLGDLK#21 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F564MLGDLK#21 meets industry standards.
7.What is the process for return or replacement of R5F564MLGDLK#21?
All R5F564MLGDLK#21 units undergo pre-shipment inspection (PSI). If there is an issue with R5F564MLGDLK#21, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F564MLGDLK#21 part is unused and in its original packaging.
Return procedure for R5F564MLGDLK#21:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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