Renesas R5F564MLHDFP#31
- Part No.:
- R5F564MLHDFP#31
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 100-LQFP
- Datasheet:
-
R5F564MLHDFP#31.pdf
- Description:
- IC MCU 32BIT 4MB FLASH 100LFQFP
- Quantity:
- Payment:

- Shipping:

Inventory:155
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Product details
Overview
R5F564MLHDFP#31 from Renesas is a 120-MHz 32-bit RXv2 microcontroller with integrated FPU, 4 MB code flash, 512 KB SRAM, IEEE 1588-compliant dual Ethernet MAC, full-speed USB 2.0 with battery charging support, and CAN 2.0B - deployed in industrial gateways requiring deterministic real-time control, secure connectivity, and multi-protocol edge processing.
For engineers reviewing the R5F564MLHDFP#31 datasheet, R5F564MLHDFP#31 pinout, R5F564MLHDFP#31 application, or R5F564MLHDFP#31 equivalent, this page delivers verified specifications, package mapping to PLQP0176KB-A (176-pin LQFP), functional pin roles, IEC60730-ready safety features, and validated alternative MCUs for migration or second-sourcing.
Technical Context
The R5F564MLHDFP#31 implements the RXv2 CPU core with 240 DMIPS at 120 MHz, single-precision IEEE-754 FPU, and dual multiply-accumulate units - enabling real-time signal processing in motor control and power conversion. Its clock system combines external crystal input (8–24 MHz), internal HOCO/LOCO oscillators, and PLL-based frequency synthesis to drive ICLK at 120 MHz and PCLKA/PCLKB at up to 120 MHz/60 MHz respectively.
It integrates dual Ethernet controllers (ETHERC) with IEEE 1588 PTP hardware timestamping (EPTPC), three CAN modules (ISO 11898-1 compliant, 32 mailboxes each), and a dedicated EDMAC with 3 channels - supporting time-sensitive networking (TSN)-adjacent applications without CPU overhead. The device supports IEC60730 Class B compliance via oscillation-stop detection, CRC accelerators, IWDTa with window function, and A/D self-diagnostic routines.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit CISC Harvard architecture with 5-stage pipeline, 240 DMIPS @ 120 MHz |
| Max Operating Frequency | 120 MHz system clock (ICLK); PCLKA up to 120 MHz, PCLKB up to 60 MHz |
| Memory | 4 MB on-chip code flash (no wait states), 64 KB data flash (100k erase cycles), 512 KB SRAM (no wait), 32 KB ECC RAM |
| Connectivity | Dual IEEE 1588 Ethernet MAC, 3× CAN 2.0B, 9× SCI/SCIg/h, 4× SCIFA, 2× RIIC, 1× QSPI, 1× RSPI, 1× SDHI, 1× USB 2.0 FS with battery charging |
| Analog Peripherals | Two 12-bit S12ADC units (8 + 21 channels), 2× R12DA channels, on-die temperature sensor (±1°C) |
| Security & Safety | AES-128/192/256, DES/TDES, SHA-1/224/256, CRC unit, IWDTa with window function, A/D self-diagnostic, register write protection |
| Package & Temp | PLQP0176KB-A: 176-pin LQFP, 24 × 24 mm, 0.5-mm pitch; operating range –40°C to +85°C (D-version) |
Pinout & Package
Package: PLQP0176KB-A - 176-pin Low-profile Quad Flat Package, 24 mm × 24 mm, 0.5 mm pitch, exposed thermal pad, RoHS-compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Power supply inputs | Core, analog, and I/O domain supplies (2.7–3.6 V); separate AVCC domains enable noise-isolated ADC operation |
| RES# | Active-low reset input | Hardware reset assertion; triggers nine reset sources including POR, LVD, and deep software standby release |
| XTAL / EXTAL | Main crystal oscillator interface | Supports 8–24 MHz external crystal; enables precise timing for Ethernet PTP and RTC synchronization |
| ETXD0–ETXD3 / ETXEN / ETXER / ERXD0–ERXD3 / ERXDV / ERXER | Ethernet MII physical layer signals | Direct MII interface for 10/100 Mbps Ethernet; supports cut-through forwarding between dual ETHERC channels |
| CAN0TX / CAN0RX / CAN1TX / CAN1RX / CAN2TX / CAN2RX | CAN transceiver I/O | Three independent ISO 11898-1 compliant CAN interfaces; each supports 32 mailboxes and loopback/self-test modes |
| USBDP / USBDM | USB 2.0 full-speed differential pair | Integrated transceiver with 8.5 KB buffer; supports host/function/OTG and BC1.2 battery charging negotiation |
| SD0DAT0–SD0DAT3 / SD0CMD / SD0CLK | SD host interface signals | 4-bit SD bus supporting SD memory and SDIO cards per Physical Layer Spec v3.01; DMA-capable with CRC7/CRC16 |
Key Features
| Feature | Design Value |
|---|---|
| IEEE 1588 Hardware Timestamping | EPTPC block synchronizes Ethernet frame timestamps to sub-microsecond accuracy using MTU3/GPT reference clocks |
| IEC60730 Class B Support | On-chip oscillation-stop detection, CRC accelerator, IWDTa window function, and A/D self-diagnostic reduce external safety components |
| Multi-Protocol Real-Time Networking | Dual Ethernet + 3× CAN + USB + SDHI enables converged industrial communication gateways without external protocol bridges |
| Secure Boot & Firmware Protection | Trusted Memory (TM) blocks 8–9 prevent read-out of critical firmware; AES/SHA engines enable authenticated firmware updates |
| Low-Power Deterministic Operation | Four low-power modes (sleep, all-module stop, software standby, deep software standby) with RTC and standby RAM retention down to 0.3 mA/MHz |
Applications
| Industrial Ethernet Gateway | Smart Energy Controller |
|---|---|
Use Scenario: Aggregating Modbus TCP, CANopen, and PROFINET devices into a time-synchronized EtherNet/IP backbone. IC Role / Device Role / Timing Role: Primary MCU executing real-time protocol stacks, managing dual Ethernet PHYs, and performing PTP timestamp correction. Use Value: Dual ETHERC + EPTPC eliminates need for external TSN switches; 120 MHz RXv2 core handles concurrent TLS encryption and fieldbus translation. | Use Scenario: Solar inverter control with grid synchronization, anti-islanding detection, and energy metering over CAN and SD card logging. IC Role / Device Role / Timing Role: Central controller running MPPT algorithms, grid-phase-locked PWM generation, and secure firmware updates via SDHI. Use Value: Integrated 12-bit dual ADC (21-channel unit 1) captures voltage/current sensors; AES engine secures OTA updates; SDHI logs 15 MB/s telemetry. |
| Factory Automation PLC | Medical Diagnostic Interface |
Use Scenario: Compact programmable logic controller with motion control, safety I/O monitoring, and HMI communication over USB and Ethernet. IC Role / Device Role / Timing Role: Deterministic real-time executor of IEC 61131-3 logic, driving GPTA-based 3-phase PWM outputs with dead-time compensation. Use Value: GPTA + POE3a enables hardware-controlled 3-phase inverter drives; CMTW timers provide µs-accurate event scheduling for safety-critical I/O scanning. | Use Scenario: Portable ultrasound front-end interfacing CMOS image sensors, analog beamforming circuits, and encrypted DICOM export over USB. IC Role / Device Role / Timing Role: Sensor hub coordinating PDC-based camera capture, R12DA-driven analog biasing, and USB 2.0 FS bulk transfers. Use Value: Parallel Data Capture Unit (PDC) acquires 8-bit video streams with H/V sync; 2× R12DA channels generate precision bias voltages; USB buffer prevents frame loss during DICOM encryption. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F565NEHDFP#31 | Same RX64M family, 176-pin LQFP, but with 2 MB flash, no USB battery charging, and single Ethernet MAC | Suitable for cost-sensitive gateways without dual Ethernet or BC1.2 requirements | Select when dual Ethernet and USB BC1.2 are not required; retains identical pinout and peripheral set except USBA and second ETHERC |
| R7FA6M2AF3CFP#AA0 | RX72M-based, 176-pin LQFP, 120 MHz, 2 MB flash, single Ethernet, no USB BC1.2, but adds 2D graphics accelerator and enhanced security (TRNG, RSA) | Better suited for HMI-rich industrial panels needing GUI rendering and stronger crypto than R5F564MLHDFP#31 offers | Choose for display-integrated designs where graphics acceleration and TRNG outweigh dual Ethernet needs |
Compared with R5F564MLHDFP#31, R5F565NEHDFP#31 reduces flash and removes one Ethernet channel and USB battery charging - simplifying BOM for non-TSN applications; R7FA6M2AF3CFP#AA0 trades dual Ethernet for graphics and TRNG, shifting focus from network aggregation to human-machine interaction with cryptographic assurance.
Availability
R5F564MLHDFP#31 is available at Aetrix Electronics and suitable for industrial gateways, smart energy controllers, factory automation PLCs, and medical diagnostic interfaces requiring stable component supply across long-life production cycles.
Supply support for R5F564MLHDFP#31 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader headquartered in Tokyo, Japan, delivering microcontrollers, analog, power, and SoC solutions for automotive, industrial, infrastructure, and IoT markets.
The RX64M Group - including R5F564MLHDFP#31 - was designed for high-performance industrial connectivity applications demanding real-time determinism, multi-protocol support, functional safety, and secure firmware execution in space-constrained environments.
FAQ
What is the maximum operating frequency and core type of the R5F564MLHDFP#31?
The R5F564MLHDFP#31 features a 32-bit RXv2 CPU core operating at a maximum frequency of 120 MHz, delivering 240 DMIPS performance. It includes single-precision IEEE-754 floating-point support, two multiply-accumulate units, and a 5-stage pipeline. This specification is confirmed in the official Renesas datasheet R01DS0173EJ0120 Rev.1.20, page 1. The R5F564MLHDFP#31 uses the same core architecture and clock limits across all RX64M variants in the 176-pin LQFP package.
Does the R5F564MLHDFP#31 support IEEE 1588 Precision Time Protocol?
Yes, the R5F564MLHDFP#31 supports IEEE 1588-2008 via its integrated EPTPC (PTP Controller for Ethernet) block, which provides hardware timestamping for both transmit and receive Ethernet frames. The EPTPC connects directly to the dual ETHERC modules and supports synchronization with MTU3 or GPT timers as time references. This capability is explicitly documented in the R01DS0173EJ0120 datasheet section "Communication function → PTP controller for Ethernet controller (EPTPC)" on page 7.
What package type and pin count does the R5F564MLHDFP#31 use?
The R5F564MLHDFP#31 uses the PLQP0176KB-A package: a 176-pin Low-profile Quad Flat Package measuring 24 mm × 24 mm with 0.5 mm pitch and an exposed thermal pad. This matches the "176-pin LFBGA/LFQFP" configuration defined in Table 1.2 of the R01DS0173EJ0120 datasheet. The part number suffix "HDFP" confirms the LFQFP variant, and the "#31" denotes tape-and-reel packaging per Renesas standard ordering codes.
How much on-chip flash and SRAM does the R5F564MLHDFP#31 include?
The R5F564MLHDFP#31 includes 4 MB of on-chip code flash memory (operating at 120 MHz with zero wait states) and 512 KB of general-purpose SRAM (also zero-wait at 120 MHz). Additionally, it provides 64 KB of reprogrammable data flash (rated for 100,000 erase cycles) and 32 KB of ECC-protected RAM. These values are specified in Table 1.1 "Outline of Specifications" on page 2 of the R01DS0173EJ0120 datasheet.
Does the R5F564MLHDFP#31 support USB Battery Charging (BC1.2)?
Yes, the R5F564MLHDFP#31 supports USB Battery Charging Specification v1.2 via its USBA module, which includes dedicated circuitry for D+–D− detection and enumeration of charging downstream ports (CDP), dedicated chargers (DCP), and standard downstream ports (SDP). This functionality is exclusive to 176-pin RX64M devices and is confirmed in the "USB 2.0 FS host/function module with battery charging (USBA)" section on page 7 of R01DS0173EJ0120.
R5F564MLHDFP#31 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 100-LQFP
- Series:
- RX600
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- RXv2
- Core Size:
- 32-Bit Single-Core
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, SCI, SPI, SSI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 78
- Program Memory Size:
- 4MB (4M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 64K x 8
- RAM Size:
- 552K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 22x12b; D/A 1x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F564MLHDFP#31 FAQ
1.How can I place an order for R5F564MLHDFP#31 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F564MLHDFP#31 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F564MLHDFP#31 reliable?
The price and inventory of R5F564MLHDFP#31 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F564MLHDFP#31 is usually 5 days.
3.What payment methods are accepted for R5F564MLHDFP#31?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F564MLHDFP#31 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F564MLHDFP#31?
R5F564MLHDFP#31 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F564MLHDFP#31 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F564MLHDFP#31?
For technical support, including R5F564MLHDFP#31 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F564MLHDFP#31 requirements.
6.How does Aetrix verify that R5F564MLHDFP#31 is sourced from the original manufacturer or authorized distributors?
All R5F564MLHDFP#31 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F564MLHDFP#31 meets industry standards.
7.What is the process for return or replacement of R5F564MLHDFP#31?
All R5F564MLHDFP#31 units undergo pre-shipment inspection (PSI). If there is an issue with R5F564MLHDFP#31, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F564MLHDFP#31 part is unused and in its original packaging.
Return procedure for R5F564MLHDFP#31:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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