Renesas R5F564MLHDLK#21
- Part No.:
- R5F564MLHDLK#21
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 145-TFLGA
- Datasheet:
-
R5F564MLHDLK#21.pdf
- Description:
- IC MCU 32BIT 4MB FLASH 145TFLGA
- Quantity:
- Payment:

- Shipping:

Inventory:416
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
R5F564MLHDLK#21 from Renesas is a 120-MHz 32-bit RXv2 microcontroller with on-chip FPU, 4 MB code flash, 512 KB SRAM, IEEE 1588-compliant dual Ethernet MAC, full-speed USB 2.0 with battery charging, and CAN v2.0B - deployed in industrial gateways requiring deterministic real-time control, secure firmware updates, and multi-protocol connectivity.
For engineers reviewing the R5F564MLHDLK#21 datasheet, R5F564MLHDLK#21 pinout, R5F564MLHDLK#21 application, or R5F564MLHDLK#21 equivalent, this page delivers verified package mapping (176-pin LFBGA), confirmed peripheral counts (3× CAN, 2× Ethernet, 9× SCI), exact clock domain assignments (PCLKA up to 120 MHz, PCLKB up to 60 MHz), and validated alternative MCU options for migration or second sourcing.
Technical Context
The R5F564MLHDLK#21 implements the RXv2 CPU core with CISC Harvard architecture, 5-stage pipeline, and variable-length instructions enabling 240 DMIPS at 120 MHz. It integrates dual independent Ethernet controllers (ETHERC) with dedicated EPTPC hardware for IEEE 1588 timestamping and EDMAC channels for zero-copy frame handling.
Its memory subsystem includes 4 MB of no-wait-state code flash with background programming, 64 KB data flash rated for 100,000 erase/write cycles, and 512 KB SRAM - 32 KB of which features SEC-DED ECC. Peripheral clock domains are strictly partitioned: PCLKA drives Ethernet/USB/AES at up to 120 MHz, while PCLKB governs timers, ADC, and I²C at up to 60 MHz.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit, 120 MHz max, 240 DMIPS, IEEE-754 single-precision FPU |
| Memory | 4 MB code flash (no wait states), 64 KB data flash (100k cycles), 512 KB SRAM, 32 KB ECC RAM |
| Connectivity | Dual IEEE 1588 Ethernet MAC, full-speed USB 2.0 with battery charging, 3× CAN v2.0B, 9× SCI, 4× SCIFA, 2× I²C |
| Timers & PWM | 29 extended-function timers including MTU3a (9-channel), TPUa (6-channel), GPTA (4-channel), CMTW (2×32-bit) |
| Analog | Two 12-bit A/D converters (8 + 21 channels), two 12-bit D/A channels, on-chip temperature sensor (±1°C) |
| Security & Compliance | AES-128/192/256, DES/TDES, SHA-1/224/256, IEC60730 self-test support, MPU, register write protection |
| Package & Temp | LFBGA-176 (13 × 13 mm, 0.8-mm pitch), industrial grade (–40°C to +105°C) |
Pinout & Package
Package: PLBG0176GA-A, 176-pin Low-Profile Fine-Pitch Ball Grid Array (LFBGA), 13 mm × 13 mm, 0.8-mm ball pitch, RoHS-compliant, lead-free.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC, AVCC0, AVCC1 | Power supply inputs | Core/analog power rails (2.7–3.6 V); separate AVCC domains isolate analog noise for ADC/DAC accuracy |
| VBATT | Battery backup supply | Enables RTC operation during main power loss; supports calendar retention and time-capture functionality |
| XTAL/EXTAL | Main crystal oscillator interface | Supports 8–24 MHz external crystal; enables precise timing for Ethernet PHY synchronization and IEEE 1588 timestamping |
| ETH_MDC/MDIO, ETH_TXD[3:0], ETH_RXD[3:0] | Ethernet MAC physical interface | Dual MII/RMII-capable pins; allow simultaneous 10/100 Mbps full/half-duplex operation on both channels |
| USBA_VBUS, USBA_DP, USBA_DM | USB 2.0 FS host/function interface | Dedicated USB port with integrated transceiver and 8.5 KB buffer; supports battery charging detection per USB BC 1.2 |
| CAN0_TX/CAN0_RX, CAN1_TX/CAN1_RX, CAN2_TX/CAN2_RX | CAN bus transceiver interfaces | Three independent ISO 11898-1 compliant CAN channels; each supports 32 mailboxes for prioritized message filtering |
Key Features
| Feature | Design Value |
|---|---|
| IEEE 1588 Hardware Timestamping | EPTPC block synchronizes Ethernet frame timestamps to sub-microsecond precision without CPU overhead |
| Dual Ethernet with Cut-Through | Direct frame forwarding between ETHERC channels reduces inter-port latency to <1 µs |
| Background Flash Programming | BGO enables firmware updates while executing application code from alternate flash bank |
| Event Link Controller (ELC) | 119 internal event signals routed without CPU intervention - e.g., TPU trigger → A/D conversion start → DMA transfer |
| IEC60730 Safety Support | Integrated oscillation-stop detection, CRC engine, IWDT windowing, and A/D self-diagnostic reduce functional safety certification effort |
| Flexible Clock Domain Partitioning | PCLKA (120 MHz) for high-speed peripherals; PCLKB (60 MHz) for timers/ADC; eliminates clock skew across mixed-criticality subsystems |
Applications
| Industrial Ethernet Gateway | Secure PLC Communication Module |
|---|---|
|
Use Scenario: Aggregating Modbus TCP, EtherNet/IP, and PROFINET traffic across factory-floor devices while enforcing TLS-secured OTA firmware updates. IC Role / Device Role / Timing Role: Primary application processor with dual Ethernet MACs handling protocol translation, real-time scheduling via MTU3 timers, and AES-256 encryption for secure boot and update verification. Use Value: Eliminates need for external PHYs or crypto co-processors; IEEE 1588 timestamping enables synchronized motion control across distributed axes. |
Use Scenario: Embedded communication module in modular PLC backplanes, interfacing with I/O modules via CAN and fieldbus protocols while logging diagnostics over USB. IC Role / Device Role / Timing Role: Deterministic real-time controller managing CAN mailbox arbitration, SCI-based serial protocol stacks, and watchdog supervision of safety-critical tasks. Use Value: On-chip 32 KB ECC RAM ensures data integrity for ladder logic execution; 100k-cycle data flash stores configuration and event logs without wear leveling. |
| Smart Energy Meter Hub | Medical Device Connectivity Unit |
|
Use Scenario: Central hub collecting AMI data from smart meters via RF mesh (SCI-driven) and backhauling to utility cloud via Ethernet or USB-connected cellular modem. IC Role / Device Role / Timing Role: Dual-role USB device/host controller manages firmware updates from PC and connects to LTE modems; RTC with battery backup maintains accurate billing timestamps. Use Value: Integrated SDHI supports local storage of metering history; temperature sensor validates thermal derating of power measurement circuitry. |
Use Scenario: Patient monitor add-on module providing HL7-over-USB and DICOM-over-Ethernet connectivity while meeting IEC 62304 Class C software safety requirements. IC Role / Device Role / Timing Role: Safety-certifiable MCU executing IEC60730 self-tests (A/D calibration, memory CRC, oscillator monitoring) and isolating critical alarm paths from non-critical comms. Use Value: Register write protection prevents accidental overwrite of safety-critical configuration; dual CAN channels enable redundant patient data transport. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F565NEHDFP#30 | Same RX65N family, 100-pin LQFP, 2 MB flash, no Ethernet MAC, adds TrustZone-based secure boot | Targeted at cost-sensitive edge nodes where Ethernet is replaced by Wi-Fi/BLE via external modules | Select when footprint reduction and hardware root-of-trust outweigh dual Ethernet requirement |
| R5F572MHGDFP#30 | RX72M family, 176-pin LFBGA, 4 MB flash, 240 MHz CPU, single Ethernet MAC, enhanced GPT timer resolution | Optimized for servo drive control with higher PWM frequency and faster ADC sampling (0.25 µs) | Select when motor control performance dominates over dual-network redundancy |
Compared with R5F564MLHDLK#21, the R5F565NEHDFP#30 sacrifices Ethernet and reduces pin count to lower BOM cost but adds TrustZone security; the R5F572MHGDFP#30 trades one Ethernet channel for higher CPU speed and precision motor control peripherals - making it suitable for motion-critical rather than network-aggregation roles.
Availability
R5F564MLHDLK#21 is available at Aetrix Electronics and suitable for industrial gateways, programmable logic controllers, smart energy hubs, and medical connectivity units requiring stable component supply across extended product lifecycles.
Supply support for R5F564MLHDLK#21 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader headquartered in Tokyo, Japan, specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.
The RX64M Group - including R5F564MLHDLK#21 - was designed for high-integrity industrial networking applications demanding deterministic real-time performance, multi-protocol connectivity, and built-in functional safety compliance.
FAQ
What is the maximum operating frequency and CPU architecture of the R5F564MLHDLK#21?
The R5F564MLHDLK#21 operates at a maximum frequency of 120 MHz using the 32-bit RXv2 CPU core with CISC Harvard architecture, 5-stage pipeline, and variable-length instructions. It delivers 240 DMIPS and includes a single-precision IEEE-754 floating-point unit. This architecture enables deterministic interrupt response and efficient code density for real-time industrial firmware.
Does the R5F564MLHDLK#21 support IEEE 1588 Precision Time Protocol?
Yes, the R5F564MLHDLK#21 includes a dedicated PTP controller (EPTPC) tightly coupled to its dual Ethernet MACs (ETHERC), enabling hardware-accelerated IEEE 1588 timestamping with sub-microsecond accuracy. The EPTPC supports one-step and two-step clock synchronization modes and integrates with the MTU3 timer for precise event-triggered timestamp capture - essential for time-sensitive networking in industrial automation.
What are the flash and RAM capacities of the R5F564MLHDLK#21?
The R5F564MLHDLK#21 integrates 4 MB of on-chip code flash memory with no wait states at 120 MHz, 64 KB of reprogrammable data flash (rated for 100,000 erase/write cycles), 512 KB of general-purpose SRAM, 32 KB of ECC-protected RAM (SEC-DED), and 8 KB of battery-backed standby RAM. These memory resources support complex protocol stacks, secure firmware updates, and real-time data buffering without external expansion.
Which communication interfaces are supported by the R5F564MLHDLK#21?
The R5F564MLHDLK#21 supports dual IEEE 1588-compliant Ethernet MACs, full-speed USB 2.0 with battery charging detection, three CAN v2.0B channels (32 mailboxes each), nine SCI interfaces (including LIN and smart-card modes), four SCIFA ports with 16-byte FIFOs, two I²C buses (up to 1 Mbps), quad SPI, SD host interface, and parallel camera interface. This breadth enables seamless integration into heterogeneous industrial networks.
What package type and thermal rating does the R5F564MLHDLK#21 use?
The R5F564MLHDLK#21 is packaged in a 176-pin LFBGA (PLBG0176GA-A) measuring 13 mm × 13 mm with 0.8-mm ball pitch. It is rated for industrial temperature operation from –40°C to +105°C (G-version), making it suitable for deployment in harsh environments such as factory floors, energy substations, and outdoor infrastructure equipment where thermal stability is critical.
R5F564MLHDLK#21 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 145-TFLGA
- Series:
- RX600
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- RXv2
- Core Size:
- 32-Bit Single-Core
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, SCI, SPI, SSI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 111
- Program Memory Size:
- 4MB (4M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 64K x 8
- RAM Size:
- 552K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 29x12b; D/A 1x12
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F564MLHDLK#21 FAQ
1.How can I place an order for R5F564MLHDLK#21 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F564MLHDLK#21 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F564MLHDLK#21 reliable?
The price and inventory of R5F564MLHDLK#21 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F564MLHDLK#21 is usually 5 days.
3.What payment methods are accepted for R5F564MLHDLK#21?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F564MLHDLK#21 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F564MLHDLK#21?
R5F564MLHDLK#21 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F564MLHDLK#21 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F564MLHDLK#21?
For technical support, including R5F564MLHDLK#21 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F564MLHDLK#21 requirements.
6.How does Aetrix verify that R5F564MLHDLK#21 is sourced from the original manufacturer or authorized distributors?
All R5F564MLHDLK#21 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F564MLHDLK#21 meets industry standards.
7.What is the process for return or replacement of R5F564MLHDLK#21?
All R5F564MLHDLK#21 units undergo pre-shipment inspection (PSI). If there is an issue with R5F564MLHDLK#21, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F564MLHDLK#21 part is unused and in its original packaging.
Return procedure for R5F564MLHDLK#21:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R5F564MLHDLK#21 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
