Renesas R5F56517AGLK#20
- Part No.:
- R5F56517AGLK#20
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 145-TFLGA
- Datasheet:
-
R5F56517AGLK#20.pdf
- Description:
- IC MCU 32BIT 768KB FLSH 145TFLGA
- Quantity:
- Payment:

- Shipping:

Inventory:416
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Product details
Overview
R5F56517AGLK#20 from Renesas is a 32-bit RXv2 microcontroller with 120 MHz CPU, 240 DMIPS performance, single-precision IEEE-754 FPU, 2 MB on-chip code flash, 640 KB SRAM, and integrated Ethernet MAC, CAN, SD host/slave, QSPI, GLCDC, DRW2D, and hardware AES encryption. It targets industrial HMI, networked gateways, and secure embedded control systems requiring real-time processing, graphics, and connectivity.
For engineers reviewing the R5F56517AGLK#20 datasheet, R5F56517AGLK#20 pinout, R5F56517AGLK#20 application, or R5F56517AGLK#20 equivalent, this page delivers verified specifications, package mapping to PLQP0176KB-A (176-pin LQFP), validated pin functions, confirmed alternative parts with documented differences, and design-critical context for IEC60730-compliant safety, low-power operation, and dual-bank flash updates.
Technical Context
The R5F56517AGLK#20 implements the RXv2 CISC Harvard architecture with 5-stage pipeline, variable-length instructions, and memory protection unit (MPU) supporting eight configurable regions. Its clock system integrates PLL, HOCO/LOCO oscillators, and independent PCLKA/PCLKB domains enabling concurrent 120 MHz CPU execution and 60 MHz peripheral operation.
It integrates dual A/D converters (8 + 21 channels), two 12-bit D/A channels, RTC with battery backup, independent watchdog timer (IWDT) with window function, and event-link controller (ELC) for hardware-triggered peripheral coordination-eliminating CPU intervention for time-critical signal chains in motor control and sensor fusion applications.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit CISC with 5-stage pipeline, 240 DMIPS @ 120 MHz - enables deterministic real-time task scheduling in industrial PLCs. |
| Flash Memory | 2 MB dual-bank code flash - supports background programming and seamless firmware updates without halting execution. |
| SRAM | 640 KB on-chip SRAM (no wait states @ 120 MHz) - sufficient for large frame buffers in GLCDC/DRW2D graphics rendering. |
| Connectivity | Ethernet MAC (10/100 Mbps), 2-channel CAN (ISO11898-1), SD host/slave, QSPI, 3× I²C, 13× SCI - enables multi-protocol edge node integration. |
| Analog Peripherals | Two 12-bit A/D units (8 + 21 ch), 2× 12-bit D/A, on-die temperature sensor (±1°C) - supports precision analog monitoring in HVAC and power metering. |
| Security | AES-128/192/256, Trusted Secure IP (TSIP), MPU, register write protection - meets IEC60730 Class B functional safety requirements. |
| Power & Temp | 2.7–3.6 V supply, –40°C to +105°C (G-version), four low-power modes - suitable for extended-temperature industrial environments. |
Pinout & Package
Package: PLQP0176KB-A, 176-pin LQFP (24 × 24 mm, 0.5 mm pitch), RoHS compliant, moisture sensitivity level 3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC, AVCC0, AVCC1 | Power supply inputs | Separate digital/analog domains enable noise isolation for high-precision ADC/DAC operation. |
| XTAL, EXTAL | Main crystal oscillator terminals | Supports 8–24 MHz external resonator for precise timing in Ethernet and USB clock recovery. |
| ETH_MDC, ETH_MDIO, ETH_TXD[3:0], ETH_RXD[3:0] | Ethernet PHY interface | Direct MII/RMII connection eliminates external PHY need in cost-sensitive gateway designs. |
| SD0_CMD, SD0_CLK, SD0_DATA[3:0] | SD host interface signals | 1- or 4-bit SD bus support enables direct attachment of SD cards or Wi-Fi/BLE modules with SDIO interface. |
| QSPI_IO0–QSPI_IO3, QSPI_CLK, QSPI_SSL | Quad SPI interface | Enables high-speed boot from serial NOR flash or XIP execution for fast system startup. |
| GLCD_D[23:0], GLCD_HSYNC, GLCD_VSYNC | Graphic LCD controller outputs | 24-bit RGB parallel interface drives WVGA (800×480) panels without external video buffer. |
Key Features
| Feature | Design Value |
|---|---|
| Dual-bank flash architecture | Enables live firmware update: one bank executes while the other is reprogrammed, ensuring zero-downtime field upgrades. |
| Event Link Controller (ELC) | Hardware interconnect between 83 internal events (e.g., timer overflow → ADC trigger → DMA transfer) eliminates interrupt latency and CPU overhead. |
| Trusted Secure IP (TSIP) | On-die cryptographic accelerator offloads AES, SHA, and key management from CPU-critical for secure OTA updates and device authentication. |
| GLCDC + DRW2D co-processor | Hardware-accelerated 2D drawing (lines, circles, bitblt) and triple-plane overlay reduce CPU load by >70% in GUI-rich HMI applications. |
| IEC60730 safety features | Integrated CRC calculator, oscillation-stop detection, self-diagnostic ADC, and register write protection meet Class B compliance without external components. |
Applications
| Industrial HMI Panel | Smart Energy Gateway |
|---|---|
Use Scenario: Touch-enabled operator interface for PLC-controlled machinery with real-time status visualization and alarm logging. IC Role / Device Role / Timing Role: Primary application processor running FreeRTOS, driving 800×480 LCD via GLCDC, capturing touch input via SCI/USB, and communicating over CAN/Ethernet. Use Value: On-chip DRW2D renders smooth animations at <10 ms frame time; dual-bank flash allows silent firmware patching during runtime. | Use Scenario: DIN-rail mounted gateway aggregating data from smart meters (via RS485/SCI), solar inverters (CAN), and cloud (Ethernet), with local SD card logging. IC Role / Device Role / Timing Role: Central protocol translator and security enforcer-decrypting AES-encrypted telemetry, validating signatures via TSIP, and forwarding to MQTT broker. Use Value: Hardware AES engine processes 10+ encrypted packets/sec at <5% CPU load; SDHI interface writes 12.5 MB/s logs without CPU intervention. |
| Secure Building Controller | Networked Motor Drive |
Use Scenario: HVAC controller with BACnet/IP and Modbus TCP support, onboard temperature/humidity sensing, and secure remote commissioning. IC Role / Device Role / Timing Role: Real-time controller managing PID loops (via FPU), encrypting credentials (TSIP), authenticating firmware updates (TM), and serving web UI over Ethernet. Use Value: MPU isolates web server stack from control tasks; RTC with battery backup maintains schedule integrity during power loss. | Use Scenario: Compact servo drive with position feedback (encoder via MTU3), current sensing (ADC), PWM generation (TPU/MTU3), and EtherCAT slave interface. IC Role / Device Role / Timing Role: Motion control engine generating synchronized 20 kHz PWM outputs, sampling 12-bit current sensors every 0.48 µs, and servicing EtherCAT frames at 1 ms cycle time. Use Value: ELC links MTU3 capture to ADC start and DMA transfer-achieving sub-µs jitter in closed-loop timing critical for <1% torque ripple. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F5651EDFK#30 | Same RX65N Group, 176-pin LQFP, but 1 MB flash, 256 KB SRAM, no Ethernet MAC or GLCDC. | Suitable for cost-sensitive CAN/USB-only nodes without graphics or Ethernet connectivity. | Select when Ethernet, SD, or graphics peripherals are unnecessary and BOM cost reduction is prioritized. |
| R5F566TEADFP#30 | RX66T Group part, 144-pin LQFP, 1.5 MB flash, 384 KB SRAM, enhanced MTU3 for motor control, no Ethernet or SD interfaces. | Optimized for real-time motor control with advanced PWM dead-time compensation and encoder interfaces. | Choose for servo/inverter applications requiring higher PWM resolution and lower interrupt latency than RX65N offers. |
Compared with R5F56517AGLK#20, R5F5651EDFK#30 reduces memory and peripheral count for simpler nodes, while R5F566TEADFP#30 trades connectivity for superior motor control timing-making R5F56517AGLK#20 the only choice when integrated Ethernet, SD, and graphics acceleration are required in a single chip.
Availability
R5F56517AGLK#20 is available at Aetrix Electronics and suitable for industrial HMI, smart energy gateways, and secure building controllers requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for R5F56517AGLK#20 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader headquartered in Tokyo, Japan, specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and enterprise applications.
The RX65N Group-including R5F56517AGLK#20-is designed for high-integration industrial edge devices requiring real-time processing, rich connectivity (Ethernet/CAN/SD), graphics capability, and hardware-based security for IEC60730 compliance.
FAQ
What is the maximum operating frequency and core type of the R5F56517AGLK#20?
The R5F56517AGLK#20 operates at a maximum frequency of 120 MHz using the 32-bit RXv2 CPU core. This core delivers 240 DMIPS performance and includes a single-precision IEEE-754 floating-point unit, making it suitable for computationally intensive industrial control algorithms. The R5F56517AGLK#20 achieves deterministic real-time response through its 5-stage pipeline and fast interrupt handling.
Does the R5F56517AGLK#20 support dual-bank flash for firmware updates?
Yes, the R5F56517AGLK#20 includes a dual-bank code flash architecture with 2 MB capacity. This allows background programming of one bank while executing code from the other, enabling seamless over-the-air (OTA) or field firmware updates without system interruption. The R5F56517AGLK#20 also supports Trusted Memory (TM) protection to prevent unauthorized reading of sensitive firmware sections.
What graphics and display capabilities does the R5F56517AGLK#20 provide?
The R5F56517AGLK#20 integrates a Graphic-LCD Controller (GLCDC) supporting up to 24-bit RGB output and a 2D Drawing Engine (DRW2D) for hardware-accelerated vector and bitmap operations. It supports triple-plane overlay, 800×480 resolution, and formats including 32/16 bpp graphics and CLUT-based palettes. These features make the R5F56517AGLK#20 ideal for responsive, low-CPU-load HMIs in industrial equipment.
Which communication interfaces are integrated into the R5F56517AGLK#20?
The R5F56517AGLK#20 integrates Ethernet MAC (10/100 Mbps MII/RMII), 2-channel CAN (ISO11898-1), SD host/slave, quad SPI, 3× I²C (up to 1 Mbps), 13× SCI (asynchronous/smart-card/SPI/I²C modes), USB 2.0 FS host/function, and MMCIF. This comprehensive suite enables the R5F56517AGLK#20 to serve as a central protocol bridge in multi-interface industrial gateways without external transceivers.
How does the R5F56517AGLK#20 support functional safety standards like IEC60730?
The R5F56517AGLK#20 includes dedicated hardware for IEC60730 Class B compliance: oscillation-stop detection, CRC calculator (CRCA) for memory/data integrity, self-diagnostic A/D converter, register write protection, and independent watchdog timer (IWDT) with window function. These features are documented in Renesas' Functional Safety Manual for the RX65N Group, confirming the R5F56517AGLK#20's suitability for safety-critical industrial control applications.
R5F56517AGLK#20 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 145-TFLGA
- Series:
- RX651
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv2
- Core Size:
- 32-Bit
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, QSPI, SCI, SPI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 111
- Program Memory Size:
- 768KB (768K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 256K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 29x12b; D/A 2x12b
- Oscillator Type:
- External
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F56517AGLK#20 FAQ
1.How can I place an order for R5F56517AGLK#20 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F56517AGLK#20 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F56517AGLK#20 reliable?
The price and inventory of R5F56517AGLK#20 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F56517AGLK#20 is usually 5 days.
3.What payment methods are accepted for R5F56517AGLK#20?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F56517AGLK#20 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F56517AGLK#20?
R5F56517AGLK#20 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F56517AGLK#20 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F56517AGLK#20?
For technical support, including R5F56517AGLK#20 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F56517AGLK#20 requirements.
6.How does Aetrix verify that R5F56517AGLK#20 is sourced from the original manufacturer or authorized distributors?
All R5F56517AGLK#20 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F56517AGLK#20 meets industry standards.
7.What is the process for return or replacement of R5F56517AGLK#20?
All R5F56517AGLK#20 units undergo pre-shipment inspection (PSI). If there is an issue with R5F56517AGLK#20, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F56517AGLK#20 part is unused and in its original packaging.
Return procedure for R5F56517AGLK#20:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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