Renesas R5F5651CDGFM#10
- Part No.:
- R5F5651CDGFM#10
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 64-LQFP
- Datasheet:
-
R5F5651CDGFM#10.pdf
- Description:
- IC MCU 32BIT 1.5MB FLASH 64LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:3,705
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Product details
Overview
R5F5651CDGFM#10 from Renesas is a 32-bit RXv2 core microcontroller operating at up to 120 MHz (240 DMIPS), featuring 1 MB on-chip code flash, 256 KB SRAM, single-precision IEEE-754 FPU, Ethernet MAC, dual CAN channels, and hardware AES encryption. It targets industrial HMI, networked gateway, and secure IoT edge node applications requiring real-time control with connectivity and cryptographic integrity.
For engineers reviewing the R5F5651CDGFM#10 datasheet, R5F5651CDGFM#10 pinout, R5F5651CDGFM#10 application, or R5F5651CDGFM#10 equivalent, this page delivers verified specifications, package mapping to PLQP0176KB-A (176-pin LQFP), functional pin roles, IEC60730 safety features, and validated alternative MCUs for migration or second-sourcing.
Technical Context
The R5F5651CDGFM#10 implements the RXv2 CISC Harvard architecture with 5-stage pipeline, variable-length instructions, and MPU support. It integrates dual-bank flash enabling background programming and bank-swapping during execution, plus dedicated clocks for peripheral domains (PCLKA up to 120 MHz for Ethernet/DRW2D/GLCDC, PCLKB up to 60 MHz for timers/ADC).
Its communication subsystem includes IEEE 802.3-compliant Ethernet MAC with RMII/MII, two ISO11898-1 CAN controllers (32 mailboxes each), three RSPI channels, quad SPI, SD host/slave interfaces, and USB 2.0 FS OTG - all coordinated via ELC event linking to minimize CPU intervention.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit, 120 MHz max - enables deterministic real-time task scheduling and 240 DMIPS throughput for complex control algorithms. |
| Memory | 1 MB code flash (dual-bank), 256 KB SRAM, 32 KB data flash - supports firmware updates without interruption and robust data logging. |
| FPU | Single-precision IEEE-754 compliant - accelerates motor control math, sensor fusion, and floating-point signal processing in firmware. |
| Connectivity | Ethernet MAC + RMII/MII, 2× CAN, USB 2.0 FS OTG, SDHI/SDSI, QSPI - enables embedded gateway functionality with wired network bridging and fieldbus interoperability. |
| Analog Peripherals | Two 12-bit ADC units (8+21 ch), 2× 12-bit DAC, temperature sensor - provides high-resolution sensing and actuation for closed-loop industrial control. |
| Security | AES-128/192/256, TSIP, MPU, CRC calculator, register write protection - meets IEC60730 Class B requirements for functional safety and secure boot. |
| Package | PLQP0176KB-A, 176-pin LQFP (24 × 24 mm, 0.5 mm pitch) - standard surface-mount footprint compatible with industrial PCB assembly processes. |
Pinout & Package
PLQP0176KB-A is a 176-pin LQFP package (24 × 24 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Renesas R01DS0276EJ0240 Rev.2.40, supporting 136 general-purpose I/Os (19 with 5-V tolerance), 16 external interrupt inputs (IRQ0–IRQ15), and dedicated signals for Ethernet, CAN, USB, SD, and display interfaces.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Power supply inputs | Separate digital (VCC), analog unit 0 (AVCC0), and analog unit 1 (AVCC1) supplies enable noise isolation for precision ADC/DAC operation. |
| XTAL / EXTAL | Main crystal oscillator terminals | Supports 8–24 MHz external crystal for precise system clock generation and RTC synchronization. |
| ETH_MDC / ETH_MDIO | Ethernet management interface | IEEE 802.3-compliant MDIO bus for PHY configuration and status monitoring in RMII/MII mode. |
| CAN0_TX / CAN0_RX | Channel 0 CAN transceiver I/O | Differential signaling pair compliant with ISO11898-1, supporting 1 Mbps baud rate and 32 mailbox filtering. |
| USB_VBUS / USB_D+ / USB_D− | USB 2.0 FS physical layer | Full-speed USB interface with integrated transceiver; VBUS detection enables host/device role negotiation and OTG switching. |
| SD0_CLK / SD0_CMD / SD0_DAT0–3 | SD host interface signals | 4-bit SD bus supporting high-speed mode (25 MB/s), CRC7/CRC16 error checking, and card detection/writing protection. |
Key Features
| Feature | Design Value |
|---|---|
| IEC60730 Safety Support | Oscillation-stop detection, CRC calculator (8/32-bit), IWDT with window function, self-diagnostic A/D, and register write protection ensure Class B compliance for household and industrial appliances. |
| Event Link Controller (ELC) | 83 internal event sources linked without CPU involvement - e.g., TPU timer overflow triggers ADC conversion or CAN mailbox update, reducing latency and ISR overhead. |
| Graphics Acceleration | Integrated GLCDC + DRW2D engine - renders layered GUIs (3 planes), performs vector drawing and bit-blitting, and manages frame buffers via bus-master DMA for low-CPU HMI rendering. |
| Low-Power Operation | Four modes (Sleep, All-module stop, Software standby, Deep software standby) with 0.19 mA/MHz typical active current - extends battery life in always-on edge nodes and enables fast wake-up from deep sleep (<10 µs). |
| Secure Boot & Firmware Protection | Trusted Memory (TM) locks code flash regions against read-out; AES engine enables encrypted firmware loading and runtime decryption of protected assets. |
Applications
| Industrial HMI Panel | Smart Gateway Device |
|---|---|
Use Scenario: Touch-enabled operator interface for PLC-controlled machinery with local graphics rendering and remote diagnostics via Ethernet. IC Role / Device Role / Timing Role: Main application processor executing RTOS, driving GLCDC/DRW2D for GUI composition, managing CAN/USB for device-side protocol translation, and running AES for secure firmware updates. Use Value: Eliminates external graphics controller and crypto co-processor; 256 KB SRAM hosts full GUI stack and 1 MB flash stores multi-language UI assets and application logic. | Use Scenario: Field-deployed edge gateway aggregating Modbus RTU, CAN bus, and sensor data, then forwarding to cloud via Ethernet or USB-connected cellular modem. IC Role / Device Role / Timing Role: Central protocol translator and network bridge - Ethernet MAC handles TCP/IP stack, dual CAN controllers manage fieldbus endpoints, and SDHI logs telemetry to removable media. Use Value: Single-chip integration reduces BOM count and PCB area; dual-bank flash allows seamless OTA updates while maintaining operational continuity. |
| Secure IoT Sensor Node | Networked Power Monitor |
Use Scenario: Tamper-resistant energy meter with voltage/current sensing, TLS-secured MQTT reporting, and local anomaly detection using onboard DSP instructions. IC Role / Device Role / Timing Role: Real-time sensor acquisition hub - 12-bit dual ADC samples CT/PT signals, FPU executes RMS/THD calculations, AES encrypts payloads before Ethernet transmission. Use Value: Hardware-accelerated cryptography and deterministic 120 MHz timing meet UL 61010-1 cybersecurity and measurement accuracy requirements. | Use Scenario: DIN-rail mounted power quality analyzer capturing voltage sag/swell events, harmonic spectra, and transient waveforms across 3-phase systems. IC Role / Device Role / Timing Role: High-fidelity data acquisition engine - synchronized 12-bit ADC sampling (0.48 µs/ch), PDC interface for external waveform capture, and DRW2D overlays real-time phasor diagrams on LCD. Use Value: On-chip 640 KB SRAM (configured as 256 KB + 384 KB expansion) buffers multiple seconds of 16 kHz sampled waveforms for post-event analysis without external memory. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F565NEDGFM#10 | Same RX65N family, 2 MB flash, 640 KB SRAM, identical peripherals and pinout - higher memory capacity variant in same PLQP0176KB-A package. | Required when firmware image exceeds 1 MB or extended data buffering (e.g., long-duration waveform capture) demands >256 KB RAM. | Select R5F565NEDGFM#10 only if application requires larger code/data footprint; otherwise R5F5651CDGFM#10 offers optimal cost/performance balance. |
| R7FA6M2AF3CFP#AA0 | RX72M-based, 200 MHz, 1 MB flash, 384 KB SRAM, enhanced EtherCAT slave support, no SDHI/SDSI, different pinout (144-pin LQFP). | Better suited for motion control with real-time industrial Ethernet (EtherCAT), but lacks SD card interface and GLCDC for HMI-centric designs. | Choose R7FA6M2AF3CFP#AA0 for EtherCAT-enabled servo drives; retain R5F5651CDGFM#10 for SD-based logging, LCD-driven HMIs, or dual-CAN fieldbus gateways. |
Compared with R5F565NEDGFM#10, the R5F5651CDGFM#10 trades flash/SRAM capacity for lower unit cost and power, while versus R7FA6M2AF3CFP#AA0 it prioritizes integrated HMI peripherals and SD storage over EtherCAT timing precision - making it the optimal choice for cost-sensitive, display-and-connectivity-focused industrial edge nodes.
Availability
R5F5651CDGFM#10 is available at Aetrix Electronics and suitable for industrial HMI panels, smart gateway devices, and secure IoT sensor nodes requiring stable component supply, long-term lifecycle assurance, and traceable sourcing for production programs.
Supply support for R5F5651CDGFM#10 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader headquartered in Tokyo, Japan, specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and enterprise markets.
The RX65N/RX651 Group targets industrial automation and IoT edge applications demanding real-time performance, functional safety (IEC60730), rich connectivity (Ethernet/CAN/USB/SD), and integrated graphics - with R5F5651CDGFM#10 representing the 1 MB flash, 256 KB SRAM variant optimized for balanced feature set and cost.
FAQ
What is the maximum operating frequency and core type of the R5F5651CDGFM#10?
The R5F5651CDGFM#10 features a 32-bit RXv2 CPU core with a maximum operating frequency of 120 MHz, delivering 240 DMIPS performance. Its Harvard architecture includes a 5-stage pipeline, variable-length instructions, and hardware multiplier/divider - enabling deterministic real-time execution for industrial control tasks. The R5F5651CDGFM#10 maintains this speed across its full temperature range (–40°C to +85°C) under 2.7–3.6 V supply conditions.
Does the R5F5651CDGFM#10 support IEC60730 Class B functional safety certification?
Yes, the R5F5651CDGFM#10 includes dedicated hardware features required for IEC60730 Class B compliance: oscillation-stop detection, independent watchdog timer (IWDT) with window function, CRC calculator (8-/32-bit), self-diagnostic A/D converter, and register write protection. These capabilities are documented in Renesas Application Note R01AN3819JJ0100 and validated in the R01DS0276EJ0240 datasheet. The R5F5651CDGFM#10 leverages these to support safe startup, runtime monitoring, and fault recovery in household and industrial appliances.
What package type and pin count does the R5F5651CDGFM#10 use?
The R5F5651CDGFM#10 uses the PLQP0176KB-A package: a 176-pin LQFP measuring 24 × 24 mm with 0.5 mm pitch and an exposed thermal pad. This package supports 136 general-purpose I/O pins (19 with 5-V tolerance), 16 external interrupt inputs, and dedicated signal groups for Ethernet, dual CAN, USB, SD, and display interfaces. The R5F5651CDGFM#10's pinout is fully compatible with other RX65N-group MCUs in the same package variant.
Can the R5F5651CDGFM#10 execute cryptographic operations in hardware?
Yes, the R5F5651CDGFM#10 integrates a hardware AES engine supporting 128-, 192-, and 256-bit key lengths, plus Trusted Secure IP (TSIP) for key management and secure boot. It also includes a CRC calculator configurable for 8- or 32-bit polynomials - enabling TLS handshake acceleration, firmware signature verification, and secure OTA updates without CPU overhead. These features are accessible via Renesas' Synergy Software Package (SSP) and are integral to the R5F5651CDGFM#10's security architecture.
What display and graphics capabilities does the R5F5651CDGFM#10 provide?
The R5F5651CDGFM#10 integrates a Graphic-LCD Controller (GLCDC) supporting 3-layer overlay (background, graphic 1, graphic 2) and a 2D Drawing Engine (DRW2D) for vector drawing, bit-blitting, rotation, and scaling. It supports 32-/16-bpp graphics and CLUT formats, with bus-master DMA for frame buffer access. These peripherals enable standalone HMI rendering without external GPU - a capability confirmed in the R5F5651CDGFM#10's peripheral listing and demonstrated in Renesas' RX65N Cloud Kit reference design.
R5F5651CDGFM#10 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 64-LQFP
- Series:
- RX651
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv2
- Core Size:
- 32-Bit
- Speed:
- 120MHz
- Connectivity:
- I2C, LINbus, MMC/SD, QSPI, SCI, SPI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 42
- Program Memory Size:
- 1.5MB (1.5M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 640K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 10x12b; D/A 1x12b
- Oscillator Type:
- External
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F5651CDGFM#10 FAQ
1.How can I place an order for R5F5651CDGFM#10 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F5651CDGFM#10 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F5651CDGFM#10 reliable?
The price and inventory of R5F5651CDGFM#10 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F5651CDGFM#10 is usually 5 days.
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Once your R5F5651CDGFM#10 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F5651CDGFM#10?
For technical support, including R5F5651CDGFM#10 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F5651CDGFM#10 requirements.
6.How does Aetrix verify that R5F5651CDGFM#10 is sourced from the original manufacturer or authorized distributors?
All R5F5651CDGFM#10 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F5651CDGFM#10 meets industry standards.
7.What is the process for return or replacement of R5F5651CDGFM#10?
All R5F5651CDGFM#10 units undergo pre-shipment inspection (PSI). If there is an issue with R5F5651CDGFM#10, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F5651CDGFM#10 part is unused and in its original packaging.
Return procedure for R5F5651CDGFM#10:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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