My Inquiry
My Account
Renesas R5F5651CHGBP#20
- Part No.:
- R5F5651CHGBP#20
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 64-TFBGA
- Datasheet:
-
R5F5651CHGBP#20.pdf
- Description:
- IC MCU 32BIT 1.5MB FLASH 64TFBGA
- Quantity:
- Payment:
- Shipping:
Inventory:490
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
R5F5651CHGBP#20 from Renesas is a 32-bit RXv2 microcontroller operating at up to 120 MHz, delivering 240 DMIPS with integrated single-precision IEEE-754 FPU, 2 MB on-chip code flash memory (dual-bank), 640 KB SRAM, and hardware AES-128/192/256 encryption. It integrates Ethernet MAC, CAN 2.0B (2 channels), SD host/slave interfaces, QSPI, GLCDC, DRW2D, and RTC - targeting industrial HMI, networked gateway, and secure embedded control applications.
For engineers reviewing the R5F5651CHGBP#20 datasheet, R5F5651CHGBP#20 pinout, R5F5651CHGBP#20 application, or R5F5651CHGBP#20 equivalent, key selection considerations include its 176-pin LFBGA package (PLQP0176KB-A), -40°C to +105°C G-grade operation, dual-bank flash for safe firmware updates, and integrated security IP (TSIP) supporting IEC60730 Class B compliance.
Technical Context
The R5F5651CHGBP#20 implements the RXv2 CPU core with Harvard architecture, 5-stage pipeline, and variable-length instructions enabling ultra-compact code density. It supports little- or big-endian data arrangement and includes MPU for memory protection plus Trusted Memory (TM) to restrict code fetch access to protected flash regions.
Its clock system combines external crystal (8–24 MHz), internal HOCO (16/18/20 MHz), LOCO (240 kHz), and PLL for flexible domain-specific clocking: ICLK up to 120 MHz for CPU/PCLKA peripherals (ETHERC, GLCDC, DRW2D), PCLKB up to 60 MHz for timers and ADC, and dedicated IWDT clock at 120 kHz.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit CISC with 5-stage pipeline, 240 DMIPS @ 120 MHz |
| Max Operating Frequency | 120 MHz system clock (ICLK); enables real-time deterministic execution in motor control and protocol stacks |
| Flash Memory | 2 MB code flash with dual-bank structure - allows background programming and seamless bank switching during runtime |
| SRAM | 640 KB total: 256 KB main RAM + 384 KB expansion RAM, all zero-wait-state at 120 MHz |
| Analog Peripherals | Two 12-bit A/D converters (8 + 21 channels), two 12-bit D/A channels, on-chip temperature sensor (±1°C) |
| Security Features | AES-128/192/256 engine + Trusted Secure IP (TSIP) for key management, encrypted boot, and tamper-resistant firmware |
| Package & Temp Range | PLQP0176KB-A: 176-pin LFBGA, 24 × 24 mm, 0.5-mm pitch; industrial G-grade (–40°C to +105°C) |
Pinout & Package
Package: PLQP0176KB-A - 176-pin low-profile fine-pitch ball grid array (LFBGA), 24 mm × 24 mm, 0.5 mm pitch, lead-free, RoHS-compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Power supply inputs | Separate digital (VCC) and analog (AVCC0/AVCC1) rails enable noise isolation for precision ADC/DAC operation |
| VBATT | Battery backup supply | Provides power to RTC during main supply loss - maintains calendar/timekeeping without external circuitry |
| XTAL / EXTAL | Main crystal oscillator terminals | Supports 8–24 MHz external crystal for high-accuracy system timing and Ethernet PHY synchronization |
| MD0 / MD1 | Mode setting pins | Determine boot mode (SCI/USB/FINE) and chip configuration at reset - critical for production programming flow |
| ETH_MDC / ETH_MDIO | PHY management interface | IEEE 802.3-compliant MII/RMII management interface for configuring external Ethernet PHY devices |
| SD0_CMD / SD0_CLK / SD0_DAT[0:3] | SD host interface signals | 4-bit SD bus supporting high-speed mode (25 MB/s) - enables direct connection to SD cards or Wi-Fi modules |
Key Features
| Feature | Design Value |
|---|---|
| Integrated Graphics Subsystem | GLCDC + DRW2D enables full-color LCD display with hardware-accelerated 2D rendering (bitblt, rotation, vector draw) without external GPU |
| Dual-Bank Flash Architecture | Enables over-the-air (OTA) firmware updates with zero downtime - one bank executes while the other is reprogrammed |
| IEC60730 Safety Support | Includes CRC calculator (CRCA), oscillation-stop detection, self-diagnostic A/D, register write protection, and IWDT windowing for Class B certification |
| Flexible Communication Matrix | 2× CAN, 13× SCI (including LIN-capable SCIh), 3× RSPI, QSPI, USB 2.0 FS host/function, SDHI/SDSI, MMCIF - consolidates multi-protocol gateway design |
| Hardware Cryptographic Engine | TSIP block provides secure key storage, AES encryption/decryption, and RNG - eliminates need for external secure element in IoT edge nodes |
Applications
| Industrial HMI Panel | Smart Gateway Controller |
|---|---|
Use Scenario: Standalone touch-enabled operator interface for PLC-controlled machinery with local data logging and remote diagnostics. IC Role / Device Role / Timing Role: Main application processor managing TFT-LCD via GLCDC, executing real-time control logic, and handling Modbus TCP over Ethernet. Use Value: Integrated DRW2D accelerates UI rendering; dual-bank flash enables field-upgradable firmware; TSIP secures remote access credentials. |
Use Scenario: Protocol translation hub connecting CAN-based automotive subsystems to cloud via Ethernet/Wi-Fi using SDIO-connected wireless module. IC Role / Device Role / Timing Role: Central protocol bridge running CAN-to-TCP/IP stack, managing SD host interface for wireless co-processor, and synchronizing time via RTC. Use Value: Dual CAN channels handle multiple vehicle networks; SDHI supports high-bandwidth Wi-Fi co-processor; 120 MHz CPU ensures low-latency packet forwarding. |
| Secure Edge Node | Networked Energy Meter |
Use Scenario: Tamper-resistant smart meter with encrypted firmware, secure OTA updates, and cryptographic signing of consumption data before transmission. IC Role / Device Role / Timing Role: Root-of-trust MCU performing AES-encrypted data sealing, TSIP-managed key lifecycle, and RTC-stamped event logging. Use Value: On-chip TSIP prevents firmware extraction; dual-bank flash guarantees atomic update rollback; 12-bit ADC monitors voltage/current with self-diagnostic validation. |
Use Scenario: DIN-rail mounted energy monitor with Ethernet backhaul, local LCD display, and isolated CAN for sub-metering of HVAC and lighting circuits. IC Role / Device Role / Timing Role: System-on-chip managing 12-bit A/D sampling across 21 channels, driving monochrome LCD via GLCDC, and maintaining precise billing time via RTC. Use Value: 21-channel S12AD unit captures multi-phase voltage/current simultaneously; RTC with battery backup ensures accurate time-of-use billing; CAN interface enables distributed sensor integration. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F5651EHGBP#20 | Same RX651 Group silicon, identical pinout and peripherals, but rated for –40°C to +85°C (D-grade) instead of +105°C (G-grade) | Suitable for commercial/indoor environments where extended temperature range is not required | Select when ambient operating temperature remains ≤ +85°C and cost optimization is prioritized over thermal margin |
| R5F5661CHGBP#20 | RX661 Group successor: higher 160 MHz CPU, enhanced TSIP-Lite, additional CAN FD support, same 176-pin LFBGA footprint | Required for CAN FD adoption, higher throughput crypto, or future-proofing against performance scaling needs | Choose when new designs demand CAN FD, >240 DMIPS, or next-generation security features - not drop-in compatible due to peripheral register changes |
Compared with R5F5651CHGBP#20, the R5F5651EHGBP#20 offers identical functionality at lower thermal grade, reducing cost for non-extended environments; the R5F5661CHGBP#20 delivers architectural upgrades (CAN FD, 160 MHz) but requires firmware adaptation - neither is pin-compatible replacement, though both share the same package outline and core peripheral set.
Availability
R5F5651CHGBP#20 is available at Aetrix Electronics and suitable for industrial HMI, secure edge node deployment, and networked energy metering requiring stable component supply across long product lifecycles.
Supply support for R5F5651CHGBP#20 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.
The R5F5651CHGBP#20 belongs to the RX651 Group - designed specifically for high-integration industrial human-machine interfaces and secure networked controllers requiring graphics acceleration, dual-bank flash, and IEC60730 safety features.
FAQ
What is the maximum operating frequency and CPU performance of the R5F5651CHGBP#20?
The R5F5651CHGBP#20 operates at a maximum system clock frequency of 120 MHz and delivers 240 DMIPS of processing performance using the RXv2 CPU core. Its single-precision IEEE-754 floating-point unit (FPU), dual multiply-accumulate units, and 5-stage pipeline enable deterministic real-time execution for motor control, protocol stacks, and graphics rendering - all verified in the official R01DS0276EJ0240 datasheet.
Does the R5F5651CHGBP#20 support secure firmware updates and cryptographic operations?
Yes, the R5F5651CHGBP#20 integrates hardware AES-128/192/256 encryption and the Trusted Secure IP (TSIP) module for secure key management, encrypted boot, and tamper-resistant firmware storage. Its dual-bank flash architecture allows background programming and atomic bank switching - enabling safe over-the-air (OTA) updates without interrupting application execution. These capabilities are documented in Section 1.1 and Chapter 32 of the R01DS0276EJ0240 datasheet.
What display and graphics capabilities does the R5F5651CHGBP#20 provide?
The R5F5651CHGBP#20 includes a Graphic-LCD Controller (GLCDC) supporting up to three overlay planes and a 2D Drawing Engine (DRW2D) capable of bitblt, rotation, vector drawing, and texture mapping. It supports 32-/16-/8-bit pixel formats and CLUT-based color conversion - enabling full-color TFT-LCD interfaces up to VGA resolution without external graphics ICs. This is confirmed in Sections 1.1 and 27–28 of the R01DS0276EJ0240 datasheet.
Which communication interfaces are integrated into the R5F5651CHGBP#20?
The R5F5651CHGBP#20 integrates Ethernet MAC (10/100 Mbps MII/RMII), 2-channel CAN 2.0B (32 mailboxes each), 13-channel SCI (including LIN-capable), 3-channel RSPI, QSPI, USB 2.0 FS host/function, SD host/slave (SDHI/SDSI), and MMCIF. These interfaces are fully supported in the RX651 Group silicon and validated per Table 1.2 and Sections 17–26 of the R01DS0276EJ0240 datasheet.
What is the package type and temperature grade of the R5F5651CHGBP#20?
The R5F5651CHGBP#20 uses the PLQP0176KB-A package: a 176-pin low-profile fine-pitch ball grid array (LFBGA), 24 mm × 24 mm, 0.5 mm pitch. It is rated for the industrial G-grade temperature range of –40°C to +105°C, making it suitable for harsh environments such as factory automation and outdoor energy infrastructure - as specified on page 1 of the R01DS0276EJ0240 datasheet.
R5F5651CHGBP#20 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 64-TFBGA
- Series:
- RX651
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv2
- Core Size:
- 32-Bit
- Speed:
- 120MHz
- Connectivity:
- I2C, LINbus, MMC/SD, QSPI, SCI, SPI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 41
- Program Memory Size:
- 1.5MB (1.5M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 640K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 10x12b; D/A 1x12b
- Oscillator Type:
- External
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F5651CHGBP#20 FAQ
1.How can I place an order for R5F5651CHGBP#20 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F5651CHGBP#20 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F5651CHGBP#20 reliable?
The price and inventory of R5F5651CHGBP#20 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F5651CHGBP#20 is usually 5 days.
3.What payment methods are accepted for R5F5651CHGBP#20?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F5651CHGBP#20 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F5651CHGBP#20?
R5F5651CHGBP#20 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F5651CHGBP#20 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F5651CHGBP#20?
For technical support, including R5F5651CHGBP#20 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F5651CHGBP#20 requirements.
6.How does Aetrix verify that R5F5651CHGBP#20 is sourced from the original manufacturer or authorized distributors?
All R5F5651CHGBP#20 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F5651CHGBP#20 meets industry standards.
7.What is the process for return or replacement of R5F5651CHGBP#20?
All R5F5651CHGBP#20 units undergo pre-shipment inspection (PSI). If there is an issue with R5F5651CHGBP#20, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F5651CHGBP#20 part is unused and in its original packaging.
Return procedure for R5F5651CHGBP#20:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R5F5651CHGBP#20 Tags
-
ATTINY4-TSHR
Microchip Technology
-
ATTINY10-TSHR
Microchip Technology
-
ATTINY10-TS8R
Microchip Technology
-
ATTINY202-SSNR
Microchip Technology
-
ATTINY202-SSFR
Microchip Technology
-
ATTINY402-SSNR
Microchip Technology
-
PIC16F15213T-I/MF
Microchip Technology
-
PIC16F15213-E/MF
Microchip Technology
-
PIC10F200T-I/OT
Microchip Technology
-
ATTINY412-SSNR
Microchip Technology
-
PIC10F202T-I/OT
Microchip Technology
-
ATTINY404-SSNR
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
