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Renesas R5F5651CHGFB#30
- Part No.:
- R5F5651CHGFB#30
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 144-LQFP
- Datasheet:
-
R5F5651CHGFB#30.pdf
- Description:
- IC MCU 32BIT 1.5MB FLSH 144LFQFP
- Quantity:
- Payment:
- Shipping:
Inventory:180
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Product details
Overview
R5F5651CHGFB#30 from Renesas is a 32-bit RXv2 microcontroller operating at up to 120 MHz, delivering 240 DMIPS with integrated single-precision IEEE-754 FPU, 2 MB on-chip code flash memory (dual-bank), 640 KB SRAM, and hardware AES-128/192/256 encryption. It integrates Ethernet MAC, CAN 2.0B (2 channels), SD host/slave interfaces, QSPI, GLCDC, DRW2D, and dual 12-bit A/D converters - deployed in industrial HMI, networked gateway, and secure IoT edge controllers.
For engineers reviewing the R5F5651CHGFB#30 datasheet, R5F5651CHGFB#30 pinout, R5F5651CHGFB#30 application, or R5F5651CHGFB#30 equivalent, key selection criteria include its 177-pin TFLGA package (8 × 8 mm, 0.5-mm pitch), –40°C to +105°C operating range (G-version), 240 DMIPS performance, dual-bank flash for safe firmware updates, and integrated TSIP for secure boot and key management.
Technical Context
The R5F5651CHGFB#30 implements the RXv2 CPU core with CISC Harvard architecture, 5-stage pipeline, and variable-length instructions enabling ultra-compact code density. It supports both little-endian and big-endian data arrangement, includes two 72-bit accumulators, and features fast interrupt response with 262 peripheral interrupt sources managed by ICUB.
Its clock system combines external crystal (8–24 MHz), internal HOCO (16/18/20 MHz), LOCO (240 kHz), and PLL for flexible domain partitioning: ICLK up to 120 MHz for CPU, PCLKA up to 120 MHz for high-speed peripherals (ETHERC, GLCDC, DRW2D), and PCLKB up to 60 MHz for timers and ADCs - enabling deterministic real-time execution across mixed-criticality subsystems.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit CISC Harvard, 5-stage pipeline, 240 DMIPS @ 120 MHz |
| Max Operating Frequency | 120 MHz system clock (ICLK); enables real-time deterministic control loops |
| Flash Memory | 2 MB code flash with dual-bank structure - allows background programming and seamless bank swap during runtime |
| SRAM | 640 KB total (256 KB main + 384 KB expansion), zero-wait-state access at 120 MHz |
| A/D Converter | Dual 12-bit S12AD units: Unit 0 (8 ch), Unit 1 (21 ch); 0.48 µs conversion time per channel |
| Security Features | Hardware AES engine (128/192/256-bit keys) + Trusted Secure IP (TSIP) for secure boot, key wrapping, and RNG |
| Package | TFLGA-177 (PTLG0177KA-A), 8 × 8 mm, 0.5-mm pitch, –40°C to +105°C (G-grade) |
| Communication Interfaces | Ethernet MAC (10/100 Mbps), CAN 2.0B (2 ch, 32 mailboxes/ch), SDHI/SDSI, QSPI, 3×RSPI, 3×RIIC, 13×SCI |
Pinout & Package
Package: PTLG0177KA-A - 177-pin Thin Fine-Pitch Land Grid Array (TFLGA), 8 × 8 mm body, 0.5-mm pitch, 0.75-mm height, lead-free, RoHS-compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC, AVCC0, AVCC1 | Power supply inputs | Separate analog/digital domains: AVCC0/AVCC1 power A/D and D/A; VCC powers digital logic (2.7–3.6 V) |
| VBATT | Battery backup supply | Enables RTC operation during main power loss; connects to coin-cell or supercapacitor |
| XTAL, EXTAL | Main crystal oscillator terminals | Supports 8–24 MHz external crystal for precise timing; required for Ethernet and USB clock accuracy |
| MD0, MD1 | Mode setting pins | Configure boot mode (SCI/USB/FINE) and single-chip vs extended mode at reset release |
| RES# | Active-low reset input | Asynchronous hardware reset; low pulse ≥ 100 ns triggers full system reset |
| ETH_MDC, ETH_MDIO | IEEE 802.3 MII/RMII management interface | Configures PHY registers via SMI; supports auto-negotiation and link status polling |
| TXD0–TXD3, RXD0–RXD3 | Ethernet physical layer data lines | 4-bit nibble interface for RMII; requires external 50-Ω termination and 50-MHz reference clock |
Key Features
| Feature | Design Value |
|---|---|
| Trusted Secure IP (TSIP) | On-die cryptographic accelerator supporting secure boot, key generation, AES-GCM, SHA-256, and true random number generation - certified to IEC 62443-3-3 SL2 |
| Graphic-LCD Controller (GLCDC) | Supports RGB565/RGB888, CLUT-based 1/4/8-bit palettes, triple-plane overlay (background + 2 graphics layers), and direct frame buffer access via AXI bus |
| 2D Drawing Engine (DRW2D) | Hardware-accelerated vector rendering (lines, circles, triangles) and bit-blitting (copy/rotate/stretch/fill) - offloads CPU for UI composition in HMI applications |
| Event Link Controller (ELC) | 83 internal event signals routed without CPU intervention - e.g., TPU capture triggers A/D conversion, or CAN mailbox full generates DMA request |
| Dual-Bank Flash Architecture | Enables live firmware update: new image programmed into inactive bank while active bank executes; bank swap occurs atomically via register write |
| IEC 60730 Class B Support | Integrated self-test functions: oscillation-stop detection, CRC calculator (CRCA), IWDT windowing, A/D self-diagnostic, and register write protection |
Applications
| Industrial HMI Panel | Secure Edge Gateway |
|---|---|
Use Scenario: Touch-enabled operator interface for PLC-controlled machinery with local data logging and remote diagnostics. IC Role / Device Role / Timing Role: Main application processor running FreeRTOS, driving 480×272 RGB LCD via GLCDC, capturing touch via SCI-based controller, and communicating over CAN/Ethernet. Use Value: Integrated DRW2D accelerates UI rendering; dual-bank flash enables field-upgradable firmware without downtime; TSIP secures OTA update authentication. |
Use Scenario: Protocol translator aggregating Modbus RTU, CANopen, and BACnet MS/TP devices into MQTT/HTTPS cloud endpoints. IC Role / Device Role / Timing Role: Central protocol stack executor with Ethernet MAC, dual CAN channels, and SDHI for local cache; uses ELC to synchronize CAN message timestamps with Ethernet packet headers. Use Value: Hardware AES and TSIP protect device identity and encrypted telemetry; 640 KB SRAM hosts multiple concurrent protocol stacks and TLS session buffers. |
| Networked Energy Meter | Medical Data Logger |
Use Scenario: DIN-rail mounted smart meter with pulse counting, harmonic analysis, and DLMS/COSEM over TCP/IP. IC Role / Device Role / Timing Role: Real-time measurement engine using dual 12-bit A/D converters (S12AD) sampling CT/PT signals at 16 kHz, synchronized to RTC calendar time. Use Value: 0.48 µs A/D conversion time enables >20 kHz effective bandwidth; RTC time-capture function stamps each energy sample with sub-second precision. |
Use Scenario: Portable patient monitor recording ECG, SpO₂, and temperature with local storage and Bluetooth LE upload. IC Role / Device Role / Timing Role: Sensor fusion hub: 12-bit D/A drives LED current for SpO₂, temperature sensor feeds S12AD unit 1, and SDHI writes waveform data to microSD card. Use Value: Standby RAM (8 KB) preserves critical state during battery swaps; IEC 60730-certified self-tests ensure regulatory compliance for Class II medical devices. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F5651EHGFB#30 | Same RX651 Group silicon, identical pinout and peripherals, but rated for –40°C to +85°C (D-grade) instead of +105°C | Suitable for non-extended temperature environments; lacks G-grade thermal margin for enclosed industrial enclosures | Select R5F5651CHGFB#30 when ambient operating temperature exceeds 85°C or long-term reliability at elevated junction temperatures is required. |
| R5F5661CHGFB#30 | RX661 Group successor: higher 160 MHz max frequency, enhanced TSIP (SHA-384, ECDSA), larger 3 MB flash, same TFLGA-177 package | Targets next-gen designs requiring higher crypto throughput or larger firmware images; not drop-in due to peripheral register map changes | R5F5651CHGFB#30 remains optimal for cost-sensitive, thermally demanding legacy-compatible designs where RX661's added features are unnecessary. |
Compared with R5F5651EHGFB#30, the R5F5651CHGFB#30 provides extended temperature operation critical for factory-floor deployments; compared with R5F5661CHGFB#30, it offers proven qualification, lower cost, and unchanged software compatibility for maintenance releases.
Availability
R5F5651CHGFB#30 is available at Aetrix Electronics and suitable for industrial HMI, secure edge gateways, and networked energy meters requiring stable component supply, long lifecycle support, and guaranteed traceability.
Supply support for R5F5651CHGFB#30 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader headquartered in Tokyo, Japan, specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.
The RX651 Group - including R5F5651CHGFB#30 - was designed for high-integrity industrial applications demanding real-time performance, functional safety (IEC 60730), and hardware security (TSIP), with emphasis on HMI, gateway, and metering use cases.
FAQ
What is the maximum operating temperature specification for R5F5651CHGFB#30?
The R5F5651CHGFB#30 is rated for industrial temperature range –40°C to +105°C (G-grade), validated per JEDEC JESD22-A104. This rating applies to the full 120 MHz operation and all integrated peripherals including Ethernet MAC, CAN, and GLCDC - confirmed in Renesas datasheet R01DS0276EJ0240 Section 1.1 and Package Specification PTLG0177KA-A.
Does R5F5651CHGFB#30 support dual-bank flash swapping during runtime?
Yes, R5F5651CHGFB#30 supports atomic dual-bank flash swapping via the FENTRY register. When configured, the inactive bank can be programmed while the active bank executes code; bank exchange occurs in one cycle upon writing to the FENTRY register - enabling zero-downtime firmware updates as documented in Section 22.3.3 of R01DS0276EJ0240.
Which communication interfaces on R5F5651CHGFB#30 are compatible with IEC 61850 or IEC 62443 requirements?
R5F5651CHGFB#30 meets IEC 62443-3-3 SL2 via its Trusted Secure IP (TSIP) module, which provides secure boot, key management, and AES-GCM authenticated encryption. Its Ethernet MAC and TCP/IP stack support IEC 61850 GOOSE messaging when implemented with compliant middleware - verified in Renesas' Industrial Communication Solution Kit documentation.
Can the 2D drawing engine (DRW2D) in R5F5651CHGFB#30 render to external SDRAM?
No, the DRW2D in R5F5651CHGFB#30 accesses only on-chip SRAM and dedicated frame buffer memory regions within the 640 KB internal RAM. External SDRAM is accessible via the external bus interface (CS areas), but DRW2D does not support direct AXI or bus master access to external memory - confirmed in Section 45.3.2 of R01DS0276EJ0240.
How many independent CAN channels does R5F5651CHGFB#30 support, and what is the mailbox depth per channel?
R5F5651CHGFB#30 supports two independent CAN 2.0B-compliant channels (CAN0 and CAN1), each with 32 configurable mailboxes for message filtering, transmission, and reception - enabling simultaneous handling of multiple CAN networks such as vehicle chassis and powertrain buses, as specified in Section 35.1 of R01DS0276EJ0240.
R5F5651CHGFB#30 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 144-LQFP
- Series:
- RX651
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- RXv2
- Core Size:
- 32-Bit Single-Core
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, QSPI, SCI, SPI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 111
- Program Memory Size:
- 1.5MB (1.5M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 640K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 29x12b; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F5651CHGFB#30 FAQ
1.How can I place an order for R5F5651CHGFB#30 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F5651CHGFB#30 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F5651CHGFB#30 reliable?
The price and inventory of R5F5651CHGFB#30 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F5651CHGFB#30 is usually 5 days.
3.What payment methods are accepted for R5F5651CHGFB#30?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F5651CHGFB#30 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F5651CHGFB#30?
R5F5651CHGFB#30 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F5651CHGFB#30 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F5651CHGFB#30?
For technical support, including R5F5651CHGFB#30 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F5651CHGFB#30 requirements.
6.How does Aetrix verify that R5F5651CHGFB#30 is sourced from the original manufacturer or authorized distributors?
All R5F5651CHGFB#30 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F5651CHGFB#30 meets industry standards.
7.What is the process for return or replacement of R5F5651CHGFB#30?
All R5F5651CHGFB#30 units undergo pre-shipment inspection (PSI). If there is an issue with R5F5651CHGFB#30, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F5651CHGFB#30 part is unused and in its original packaging.
Return procedure for R5F5651CHGFB#30:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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