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Renesas R5F5651CHGLC#20
- Part No.:
- R5F5651CHGLC#20
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 177-TFLGA
- Datasheet:
-
R5F5651CHGLC#20.pdf
- Description:
- IC MCU 32BIT 1.5MB FLSH 177TFLGA
- Quantity:
- Payment:
- Shipping:
Inventory:319
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Product details
Overview
R5F5651CHGLC#20 from Renesas is a 32-bit RXv2 microcontroller operating at up to 120 MHz, delivering 240 DMIPS with integrated single-precision IEEE-754 FPU, 1.5 MB on-chip code flash, 640 KB SRAM (no wait states), and dual-bank flash for safe firmware updates. It integrates Ethernet MAC, CAN 2.0B (2 channels), SD host/slave, QSPI, GLCDC, DRW2D, and hardware AES-128/192/256 for industrial HMI and networked edge devices.
For engineers reviewing the R5F5651CHGLC#20 datasheet, R5F5651CHGLC#20 pinout, R5F5651CHGLC#20 application, or R5F5651CHGLC#20 equivalent, key selection criteria include its 176-pin LFBGA package (PLQP0176KB-A), -40°C to +105°C G-grade temperature range, 2.7–3.6 V supply, 12-bit dual A/D converter (29 total channels), and IEC60730-compliant safety features including CRC, IWDT, and register write protection.
Technical Context
The R5F5651CHGLC#20 implements the RXv2 CPU core with CISC Harvard architecture, 5-stage pipeline, and variable-length instructions enabling ultra-compact code density. It supports little- or big-endian data arrangement and includes MPU for memory protection across eight configurable regions down to 16-byte granularity.
Clock subsystem includes PLL with external crystal (8–24 MHz) or internal HOCO (16/18/20 MHz), plus dedicated 120-kHz LOCO for IWDT. Peripheral clocks are independently configurable: PCLKA (up to 120 MHz for ETHERC/EDMAC/AES/GLCDC/DRW2D), PCLKB (up to 60 MHz for most timers and interfaces), and PCLKC/PCLKD (up to 60 MHz for dual 12-bit A/D units).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit CISC Harvard, 5-stage pipeline, 240 DMIPS @ 120 MHz |
| Max Operating Frequency | 120 MHz system clock (ICLK); enables real-time deterministic response in motor control and protocol stacks |
| Memory | 1.5 MB code flash (dual-bank), 640 KB SRAM (no wait states), 32 KB data flash (100k erase cycles) |
| Analog Peripherals | Dual 12-bit S12AD: 8-channel unit 0 + 21-channel unit 1; 0.48 µs conversion time per channel |
| Connectivity | Ethernet MAC (10/100 Mbps MII/RMII), CAN 2.0B (2 channels, 32 mailboxes each), USB 2.0 FS host/function/OTG |
| Security & Safety | AES-128/192/256, TSIP, CRCA (8/32-bit), IWDT with window function, register write protection, oscillation-stop detection |
| Package & Temp | PLQP0176KB-A (176-pin LFBGA, 24 × 24 mm, 0.5 mm pitch), G-grade: –40°C to +105°C |
Pinout & Package
Package: PLQP0176KB-A - 176-pin Low-Profile Quad Flat Package (LFBGA), 24 mm × 24 mm, 0.5 mm pitch, 136 general-purpose I/O pins (19 with 5-V tolerance), 1 dedicated input pin, full pull-up and open-drain support.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Power supply inputs | Separate analog/digital domains enable noise isolation for precision ADC operation |
| VBATT | Battery backup supply | Enables RTC operation during main power loss without external circuitry |
| XTAL / EXTAL | Main crystal oscillator terminals | Supports 8–24 MHz external resonator for precise timing and Ethernet PHY synchronization |
| MD0 / MD1 | Mode setting pins | Determine boot mode (SCI/USB/FINE) and chip configuration at reset release |
| RES# | Active-low reset input | Hardware reset assertion independent of internal voltage monitors or watchdogs |
| ETH_MDC / ETH_MDIO | PHY management interface | IEEE 802.3-compliant MDIO/MDC for configuring external Ethernet PHY registers |
| TXD0 / RXD0 | SCI0 asynchronous serial I/O | Full-duplex UART interface usable for debug console or host communication |
| CRX0 / CTX0 | CAN0 differential transceiver I/O | Direct connection to ISO11898-1 compliant CAN bus with built-in termination control |
Key Features
| Feature | Design Value |
|---|---|
| Trusted Memory (TM) Function | Protects designated code flash regions from read-out; only CPU instruction fetch allowed - critical for IP protection in certified firmware |
| Graphic-LCD Controller (GLCDC) | Supports 3-layer overlay (background + 2 graphics), 32/16 bpp, CLUT formats - eliminates external display controller in HMI designs |
| 2D Drawing Engine (DRW2D) | Hardware-accelerated vector drawing (lines, circles), bit blitting with rotation/stretching - reduces CPU load in GUI rendering |
| IEC60730 Compliance Support | Integrated self-test functions: CRC calculator, IWDT windowing, A/D self-diagnostic, oscillation-stop detection - simplifies Class B certification |
| Event Link Controller (ELC) | 83 internal event signals routed without CPU intervention - enables deterministic timer-triggered ADC sampling or PWM dead-time compensation |
Applications
| Industrial HMI Panel | Smart Gateway Device |
|---|---|
Use Scenario: Touch-enabled operator interface with graphical LCD, local data logging, and remote diagnostics over Ethernet. IC Role / Device Role / Timing Role: Main application processor executing RTOS, driving GLCDC+DRW2D for UI rendering, managing SDHI for log storage, and running TCP/IP stack on ETHERC. Use Value: Integrated 640 KB SRAM eliminates external RAM; dual-bank flash enables seamless OTA updates without service interruption. | Use Scenario: Protocol translator aggregating Modbus RTU (via SCI), CANopen (via CAN), and MQTT over Ethernet for factory floor connectivity. IC Role / Device Role / Timing Role: Central protocol bridge with real-time scheduling via ICUB interrupt controller, ELC-synchronized CAN message filtering, and Ethernet frame DMA via EDMAC. Use Value: Hardware CRC and IWDT meet functional safety requirements for industrial gateways; 120 MHz CPU handles concurrent protocol stacks with margin. |
| Secure Edge Node | Networked Motor Drive |
Use Scenario: Field-deployed sensor node performing local analytics, encrypted data upload, and secure boot verification. IC Role / Device Role / Timing Role: Trusted execution environment using TM-protected flash, AES engine for payload encryption, TSIP for key management, and CRCA for firmware integrity checks. Use Value: On-chip TSIP and AES eliminate need for external secure element - reducing BOM cost and attack surface. | Use Scenario: Compact servo drive with position feedback (encoder via MTU3 phase-counting), current sensing (S12AD), and fieldbus interface (CAN/Ethernet). IC Role / Device Role / Timing Role: Real-time motion controller generating complementary PWM via MTU3, triggering ADC sampling synchronously, and communicating status via CAN mailbox FIFOs. Use Value: Hardware dead-time insertion and automatic A/D trigger generation ensure precise, jitter-free motor commutation timing. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F565NEDFP#30 | Same RX65N family, 144-pin LFQFP, 2 MB flash, 640 KB SRAM, identical peripherals but different pinout and package size | Larger footprint (20 × 20 mm), lower I/O count (111), no Ethernet PHY layer - suited for space-constrained non-Ethernet designs | Select when board layout requires QFP, higher flash density is needed, and Ethernet PHY integration is unnecessary. |
| R5F566TEHDFP#30 | RX66T group, 144-pin LFQFP, 1.5 MB flash, 384 KB SRAM, optimized for motor control with 32-bit MTU3, 3-phase PWM, and encoder interfaces | No Ethernet MAC, no SD host/slave, no GLCDC/DRW2D - focused on high-performance motor control, not HMI or gateway use | Select when primary requirement is advanced motor control (e.g., inverters, robotics) rather than networking or graphics. |
Compared with R5F5651CHGLC#20, R5F565NEDFP#30 offers higher flash capacity in a smaller package but lacks integrated PHY and has fewer I/Os; R5F566TEHDFP#30 trades networking and graphics capability for superior motor-control timing precision and dedicated PWM resources - making it unsuitable for HMI or gateway roles despite similar core performance.
Availability
R5F5651CHGLC#20 is available at Aetrix Electronics and suitable for industrial HMIs, smart gateways, secure edge nodes, and networked motor drives requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for R5F5651CHGLC#20 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.
The RX65N Group - which includes the R5F5651CHGLC#20 - was designed specifically for industrial human-machine interfaces and networked edge devices requiring integrated graphics, Ethernet, safety compliance, and robust real-time processing.
FAQ
What is the maximum operating frequency and core type of the R5F5651CHGLC#20?
The R5F5651CHGLC#20 operates at a maximum frequency of 120 MHz using the 32-bit RXv2 CPU core. This core delivers 240 DMIPS performance and includes a single-precision IEEE-754 floating-point unit, 5-stage pipeline, and variable-length instruction set for high code density. Its architecture supports deterministic real-time execution essential for industrial control and protocol stacks.
Does the R5F5651CHGLC#20 support Ethernet connectivity, and what physical layer options does it offer?
Yes, the R5F5651CHGLC#20 integrates a full Ethernet MAC (ETHERC) supporting 10/100 Mbps operation in both full- and half-duplex modes. It supports IEEE 802.3u-compliant MII and RMII interfaces, enabling direct connection to external PHYs. The device also includes an integrated Ethernet DMA controller (EDMAC) with 2 KB transmit and receive FIFOs to offload CPU bandwidth during packet processing.
What are the memory resources available on the R5F5651CHGLC#20?
The R5F5651CHGLC#20 provides 1.5 MB of on-chip code flash memory with dual-bank structure for background programming and safe firmware updates, 640 KB of zero-wait-state SRAM, 32 KB of reprogrammable data flash rated for 100,000 erase cycles, and 8 KB of battery-backed standby RAM. These resources support complex RTOS-based applications with local data buffering and secure firmware storage.
How does the R5F5651CHGLC#20 support functional safety standards like IEC60730?
The R5F5651CHGLC#20 includes multiple hardware features for IEC60730 Class B compliance: oscillation-stoppage detection, independent watchdog timer (IWDT) with window function, CRC calculator (CRCA) for memory and data integrity, self-diagnostic A/D functionality, and register write protection. These are documented in Renesas' Functional Safety Manual R01UM0517EJ0100 and reduce software validation effort for certified industrial equipment.
What graphics and display capabilities does the R5F5651CHGLC#20 provide?
The R5F5651CHGLC#20 integrates a Graphic-LCD Controller (GLCDC) supporting 3-layer overlay (background + two graphics planes), multiple pixel formats (32/16 bpp, CLUT), and various LCD panel types. It also includes a dedicated 2D Drawing Engine (DRW2D) for hardware-accelerated vector drawing, bit blitting, rotation, and stretching - enabling responsive GUIs without external graphics processors or excessive CPU overhead.
R5F5651CHGLC#20 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 177-TFLGA
- Series:
- RX651
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv2
- Core Size:
- 32-Bit
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, QSPI, SCI, SPI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 136
- Program Memory Size:
- 1.5MB (1.5M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 640K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 29x12b; D/A 2x12b
- Oscillator Type:
- External
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F5651CHGLC#20 FAQ
1.How can I place an order for R5F5651CHGLC#20 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F5651CHGLC#20 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F5651CHGLC#20 reliable?
The price and inventory of R5F5651CHGLC#20 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F5651CHGLC#20 is usually 5 days.
3.What payment methods are accepted for R5F5651CHGLC#20?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F5651CHGLC#20 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F5651CHGLC#20?
R5F5651CHGLC#20 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F5651CHGLC#20 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F5651CHGLC#20?
For technical support, including R5F5651CHGLC#20 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F5651CHGLC#20 requirements.
6.How does Aetrix verify that R5F5651CHGLC#20 is sourced from the original manufacturer or authorized distributors?
All R5F5651CHGLC#20 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F5651CHGLC#20 meets industry standards.
7.What is the process for return or replacement of R5F5651CHGLC#20?
All R5F5651CHGLC#20 units undergo pre-shipment inspection (PSI). If there is an issue with R5F5651CHGLC#20, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F5651CHGLC#20 part is unused and in its original packaging.
Return procedure for R5F5651CHGLC#20:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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