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Renesas R5F5651CHGLK#20
- Part No.:
- R5F5651CHGLK#20
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 145-TFLGA
- Datasheet:
-
R5F5651CHGLK#20.pdf
- Description:
- IC MCU 32BIT 1.5MB FLSH 145TFLGA
- Quantity:
- Payment:
- Shipping:
Inventory:416
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Product details
Overview
R5F5651CHGLK#20 from Renesas is a 32-bit RXv2 microcontroller operating at up to 120 MHz (240 DMIPS), featuring on-chip FPU, 1.5 MB code flash, 640 KB SRAM, dual-bank flash architecture, and integrated Ethernet MAC, CAN, USB 2.0 FS, SD host/slave, QSPI, and GLCDC for industrial HMI and networked edge devices.
For engineers reviewing the R5F5651CHGLK#20 datasheet, R5F5651CHGLK#20 pinout, R5F5651CHGLK#20 application, or R5F5651CHGLK#20 equivalent, key selection criteria include its 176-pin LFBGA package (PLQP0176KB-A), -40°C to +105°C G-grade temperature rating, 2-channel CAN with 32 mailboxes per channel, 12-bit dual A/D converters (8+21 channels), and hardware encryption (AES-128/192/256 + TSIP).
Technical Context
The R5F5651CHGLK#20 implements the RXv2 CPU core with Harvard architecture, 5-stage pipeline, and IEEE-754 single-precision FPU - enabling deterministic real-time control with floating-point math. It integrates dedicated clock domains: ICLK up to 120 MHz for CPU execution, PCLKA up to 120 MHz for high-speed peripherals (ETHERC, EDMAC, AES, GLCDC), and PCLKB up to 60 MHz for timers and analog modules.
Its safety-oriented design includes MPU (8 regions), Trusted Memory (TM) for secure code execution, register write protection, CRC calculator (8-/32-bit polynomials), and IEC60730-compliant self-diagnostic functions for A/D converter, oscillator stoppage detection, and IWDT windowing - all supporting functional safety certification in industrial automation systems.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit CISC Harvard architecture with 5-stage pipeline and 240 DMIPS @ 120 MHz |
| Flash Memory | 1.5 MB code flash with dual-bank structure enabling background programming and safe firmware updates |
| RAM | 640 KB SRAM (256 KB main + 384 KB expansion) and 8 KB standby RAM with battery backup support |
| Operating Voltage | 2.7–3.6 V supply range with low-power modes including deep software standby drawing <1 µA |
| Temperature Range | G-grade: –40°C to +105°C, qualified for extended industrial and transportation applications |
| Peripheral Integration | Ethernet MAC (10/100 Mbps), 2× CAN (ISO11898-1), USB 2.0 FS host/function/OTG, SDHI/SDSI, QSPI, GLCDC, DRW2D, PDC |
| Analog Functions | Dual 12-bit A/D converters (8+21 channels), 2× 12-bit D/A converters, on-die temperature sensor (±1°C) |
| Security | AES-128/192/256, Trusted Secure IP (TSIP), memory protection unit (MPU), CRC calculator, register write protection |
Pinout & Package
Package: PLQP0176KB-A - 176-pin Low-Profile Quad Flat Package (LFBGA), 24 × 24 mm, 0.5 mm pitch, RoHS-compliant, G-grade (–40°C to +105°C).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Power supply inputs | Separate digital (VCC) and analog (AVCC0/AVCC1) rails enable noise isolation for precision ADC/DAC operation |
| VBATT | Battery backup supply | Provides power to RTC and standby RAM during main supply loss, enabling timekeeping and state retention |
| RES# | Active-low reset input | Hardware reset assertion; internal POR/LVD circuits also generate resets on voltage violations |
| EXTAL / XTAL | Main crystal oscillator terminals | Supports 8–24 MHz external crystal for precise system timing and Ethernet PHY synchronization |
| MD0 / MD1 | Mode setting pins | Configure boot mode (SCI/USB/FINE) and chip operating mode at power-on reset |
| ETXD0–ETXD3 / ETXCK / ERXD0–ERXD3 / ERXCK | Ethernet physical layer interface | MII/RMII-compatible signals for direct connection to external PHY or integrated Ethernet transceiver |
| TXD0 / RXD0 / RTS0 / CTS0 | SCI0 serial interface | Asynchronous UART interface with hardware flow control for debug, configuration, or peripheral communication |
| CAN0TX / CAN0RX / CAN1TX / CAN1RX | CAN transceiver I/O | Dedicated differential signal pairs per CAN channel; require external transceivers for bus termination and level translation |
| SD0CMD / SD0CLK / SD0DAT0–3 | SD host interface signals | 4-bit SD bus supporting high-speed mode (25 MB/s); compatible with SD memory and SDIO cards per Physical Layer Spec v3.01 |
| QSPI_IO0–3 / QSPI_CLK / QSPI_CS# | Quad SPI interface | Direct connection to quad-output serial flash memory (single/dual/quad mode) for fast code/data access |
Key Features
| Feature | Design Value |
|---|---|
| Dual-bank flash architecture | Enables seamless firmware updates without halting application execution - critical for OTA-capable industrial gateways |
| Integrated GLCDC + DRW2D | Hardware-accelerated graphic rendering (bit blitting, vector drawing, CLUT conversion) eliminates CPU load for HMI display updates |
| Event Link Controller (ELC) | 83 internal event sources routed without CPU intervention - e.g., timer-triggered ADC sampling or PWM-triggered DAC update |
| IEC60730 safety support | On-chip oscillation-stop detection, CRC calculator, IWDT windowing, and A/D self-test reduce external safety component count |
| SDHI/SDSI + MMCIF triple card interface | Single MCU supports SD memory, SDIO peripherals (Wi-Fi/BT modules), and eMMC storage - simplifying storage architecture in edge nodes |
| Trusted Secure IP (TSIP) | Hardware-accelerated AES and secure key management protect firmware integrity and encrypted communications in connected devices |
Applications
| Industrial HMI Panel | Smart Gateway Controller |
|---|---|
Use Scenario: Touch-enabled operator interface for PLC-controlled machinery with real-time status visualization and alarm logging. IC Role / Device Role / Timing Role: Main application processor executing RTOS, driving TFT-LCD via GLCDC, managing touch input via SCI/USB, and communicating with PLC over CAN/Ethernet. Use Value: Integrated DRW2D accelerates UI rendering; dual CAN channels allow simultaneous connection to multiple fieldbus networks; 640 KB SRAM hosts full GUI stack and local data buffers. | Use Scenario: Protocol-bridging gateway aggregating Modbus RTU, CANopen, and BACnet MS/TP sensors into MQTT/HTTP cloud uplinks. IC Role / Device Role / Timing Role: Central protocol translator with Ethernet/Wi-Fi (via SDIO) connectivity, multi-interface serial bridging, and secure TLS offload using TSIP. Use Value: Hardware AES encryption secures cloud payloads; SDHI supports Wi-Fi module integration; 120 MHz CPU handles concurrent protocol stacks and real-time scheduling. |
| Automotive Diagnostic Tool | Networked Energy Meter |
Use Scenario: Handheld OBD-II scanner with J1939/CAN FD diagnostics, USB-C PC interface, and local firmware updates. IC Role / Device Role / Timing Role: Host controller for dual CAN interfaces (J1939 + ISO15765), USB device enumeration, and secure firmware validation via TM-protected flash banks. Use Value: Dual CAN with 32 mailboxes per channel enables parallel vehicle bus monitoring; dual-bank flash allows validated firmware swap without downtime; G-grade temp range ensures reliability in vehicle cabins. | Use Scenario: DIN-rail mounted smart meter with pulse counting, tariff switching, RS485 Modbus, and cellular backhaul via SDIO-connected LTE module. IC Role / Device Role / Timing Role: Real-time energy computation engine interfacing with metrology ICs via SPI, managing time-of-use logic via RTC, and handling secure remote firmware updates. Use Value: On-chip RTC with battery backup maintains accurate billing timestamps; AES/TSIP secures firmware updates; 12-bit ADC channels monitor auxiliary analog inputs (temperature, voltage). |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F5651EHGLK#20 | Same RX651 Group silicon; differs only in code flash capacity (2 MB vs. 1.5 MB) and SRAM mapping (640 KB same) | Requires larger PCB footprint if migrating from R5F5651CHGLK#20 due to different flash layout; identical peripheral set and pinout | Select when firmware image exceeds 1.5 MB or when future-proofing for larger feature sets is required |
| R5F5661CHGLK#20 | RX661 Group successor: higher CPU frequency (160 MHz), enhanced TSIP (SHA-256, RSA), added CAN FD support, but no GLCDC/DRW2D | Lacks integrated graphics acceleration; requires external display controller for HMI; better suited for pure networking/control over rich UI | Choose for next-gen designs prioritizing security and throughput over embedded display capability |
Compared with R5F5651CHGLK#20, R5F5651EHGLK#20 offers more flash without changing pinout or thermal profile, while R5F5661CHGLK#20 trades graphics hardware for stronger crypto and CAN FD - making the former ideal for flash-constrained HMI upgrades and the latter for security-critical infrastructure controllers.
Availability
R5F5651CHGLK#20 is available at Aetrix Electronics and suitable for industrial HMI panels, smart gateways, automotive diagnostic tools, and networked energy meters requiring stable component supply across extended temperature ranges and long product lifecycles.
Supply support for R5F5651CHGLK#20 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.
The RX651 Group - including R5F5651CHGLK#20 - was designed for high-integration industrial edge applications demanding real-time performance, rich connectivity (Ethernet/CAN/USB/SD), and embedded graphics, with built-in safety and security features aligned to IEC60730 and IEC62443.
FAQ
What is the maximum operating frequency and DMIPS rating of the R5F5651CHGLK#20?
The R5F5651CHGLK#20 operates at a maximum frequency of 120 MHz and delivers 240 DMIPS (Dhrystone MIPS) performance. This is achieved through its optimized RXv2 CPU core with 5-stage pipeline, single-cycle 32-bit multiply, and integrated IEEE-754 floating-point unit - enabling deterministic real-time execution for industrial control algorithms and protocol stacks.
Does the R5F5651CHGLK#20 support dual-bank flash for firmware updates?
Yes, the R5F5651CHGLK#20 supports dual-bank flash architecture in its 1.5 MB code flash memory. This allows background programming of one bank while executing code from the other, enabling safe over-the-air (OTA) firmware updates without system interruption - a key requirement for unattended industrial gateways and remote HMI devices.
What display interfaces does the R5F5651CHGLK#20 integrate for HMI applications?
The R5F5651CHGLK#20 integrates a Graphic-LCD Controller (GLCDC) supporting up to three overlay planes and a 2D Drawing Engine (DRW2D) with hardware-accelerated bit blitting, vector drawing, and CLUT conversion. These peripherals directly drive TFT-LCD panels with minimal CPU overhead, making the R5F5651CHGLK#20 ideal for cost-sensitive, high-performance industrial HMIs.
How many CAN channels and mailboxes does the R5F5651CHGLK#20 provide?
The R5F5651CHGLK#20 includes two independent CAN modules compliant with ISO11898-1, each supporting 32 message mailboxes. This enables concurrent communication on separate CAN buses - for example, one for vehicle diagnostics (J1939) and another for factory floor equipment (CANopen) - without software arbitration bottlenecks.
What security features are implemented in the R5F5651CHGLK#20 for firmware protection?
The R5F5651CHGLK#20 implements multiple hardware security features: Trusted Memory (TM) to prevent code read-out from designated flash regions, AES-128/192/256 encryption engines, Trusted Secure IP (TSIP) for key management and secure boot, CRC calculator for data integrity, and register write protection to guard against runaway code corruption - collectively supporting IEC62443 compliance.
R5F5651CHGLK#20 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 145-TFLGA
- Series:
- RX651
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv2
- Core Size:
- 32-Bit
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, QSPI, SCI, SPI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 111
- Program Memory Size:
- 1.5MB (1.5M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 640K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 29x12b; D/A 2x12b
- Oscillator Type:
- External
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F5651CHGLK#20 FAQ
1.How can I place an order for R5F5651CHGLK#20 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F5651CHGLK#20 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F5651CHGLK#20 reliable?
The price and inventory of R5F5651CHGLK#20 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F5651CHGLK#20 is usually 5 days.
3.What payment methods are accepted for R5F5651CHGLK#20?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F5651CHGLK#20 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F5651CHGLK#20?
R5F5651CHGLK#20 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F5651CHGLK#20 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F5651CHGLK#20?
For technical support, including R5F5651CHGLK#20 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F5651CHGLK#20 requirements.
6.How does Aetrix verify that R5F5651CHGLK#20 is sourced from the original manufacturer or authorized distributors?
All R5F5651CHGLK#20 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F5651CHGLK#20 meets industry standards.
7.What is the process for return or replacement of R5F5651CHGLK#20?
All R5F5651CHGLK#20 units undergo pre-shipment inspection (PSI). If there is an issue with R5F5651CHGLK#20, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F5651CHGLK#20 part is unused and in its original packaging.
Return procedure for R5F5651CHGLK#20:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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