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Renesas R5F5651EDGBG#20
- Part No.:
- R5F5651EDGBG#20
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 176-LFBGA
- Datasheet:
-
R5F5651EDGBG#20.pdf
- Description:
- IC MCU 32BIT 2MB FLASH 176LFBGA
- Quantity:
- Payment:
- Shipping:
Inventory:152
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Product details
Overview
R5F5651EDGBG#20 from Renesas is a 32-bit RXv2 core microcontroller operating at up to 120 MHz (240 DMIPS), featuring 1 MB on-chip code flash, 640 KB SRAM (no wait states), single-precision IEEE-754 FPU, Ethernet MAC, dual CAN channels, SD host/slave interfaces, and hardware AES-128/192/256 encryption - deployed in industrial HMI and networked gateway applications requiring real-time control and secure connectivity.
For engineers reviewing the R5F5651EDGBG#20 datasheet, R5F5651EDGBG#20 pinout, R5F5651EDGBG#20 application, or R5F5651EDGBG#20 equivalent, this page delivers verified technical context, package mapping, functional pin roles, real-world use cases, and validated alternative options - all grounded in Renesas R01DS0276EJ0240 Rev.2.40 documentation and official package data for the PLQP0176KB-A 176-pin LFBGA.
Technical Context
The R5F5651EDGBG#20 implements the RXv2 CPU core with Harvard architecture, 5-stage pipeline, and variable-length instructions enabling ultra-compact code density. It integrates dual-bank flash supporting background programming and bank-swapping during execution - critical for fail-safe firmware updates in field-deployed systems.
Its peripheral subsystem includes an Ethernet MAC with RMII/MII support, two ISO 11898-1 CAN controllers (32 mailboxes each), and a full-featured GLCDC with DRW2D 2D drawing engine - enabling direct driving of color LCDs with hardware-accelerated graphics rendering and overlay composition without CPU overhead.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit CISC core with 5-stage pipeline, 240 DMIPS @ 120 MHz - enables deterministic real-time task scheduling and high-throughput signal processing. |
| Flash Memory | 1 MB dual-bank code flash - supports background erase/program and seamless bank switching for zero-downtime firmware updates. |
| SRAM | 640 KB on-chip SRAM (256 KB main + 384 KB expansion), no wait states @ 120 MHz - eliminates memory bottlenecks in buffer-intensive protocols like TCP/IP or video capture. |
| Real-Time Peripherals | 2× CAN 2.0B, 1× Ethernet MAC (10/100 Mbps), 1× SDHI (25 MB/s), 1× SDSI - provides native industrial networking stack support without external co-processors. |
| Analog Functions | Two 12-bit A/D converters (8 + 21 channels), 2× 12-bit D/A outputs, on-die temperature sensor (±1°C) - enables local sensor fusion and closed-loop analog control. |
| Security & Safety | AES-128/192/256, TSIP, MPU, CRC calculator, IWDT with window function - meets IEC 60730 Class B requirements for self-test and fault containment. |
| Package | PLQP0176KB-A: 176-pin LFBGA, 24 × 24 mm, 0.5-mm pitch - optimized for high I/O count (136 GPIO) and thermal performance in compact industrial enclosures. |
Pinout & Package
Package: PLQP0176KB-A - 176-pin Low-Profile Fine-Pitch Ball Grid Array (LFBGA), 24 mm × 24 mm body, 0.5 mm ball pitch, lead-free, RoHS-compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC, AVCC0, AVCC1 | Power supply inputs | Separate digital (VCC) and analog (AVCC0/AVCC1) rails enable noise isolation for precision ADC/DAC operation. |
| VBATT | Battery backup supply | Provides power to RTC and standby RAM during main supply loss - maintains timekeeping and state retention. |
| XTAL, EXTAL | Main crystal oscillator terminals | Supports 8–24 MHz external crystal for precise system clock generation and Ethernet timing compliance. |
| MD0, MD1 | Mode setting pins | Determine boot source (SCI/USB/FINE) and operating mode at reset - essential for production programming and recovery sequences. |
| ETH_MDC, ETH_MDIO, ETH_TXD[3:0], ETH_RXD[3:0], ETH_TX_EN, ETH_CRS_DV, ETH_REF_CLK | Ethernet physical interface | Direct RMII/MII connection to external PHY - eliminates need for glue logic or level-shifting in 10/100 Mbps designs. |
| CAN0_TX, CAN0_RX, CAN1_TX, CAN1_RX | CAN transceiver I/O | Dedicated differential pair routing per channel - ensures signal integrity for automotive and industrial CAN FD-capable networks. |
Key Features
| Feature | Design Value |
|---|---|
| Trusted Secure IP (TSIP) | Hardware-accelerated AES and key management - enables secure boot, encrypted firmware storage, and TLS offload without software crypto overhead. |
| Graphic-LCD Controller (GLCDC) | Supports RGB565/RGB888, 3-layer overlay, and 16/32 bpp - drives QVGA–XGA panels directly, reducing external frame buffer memory by ≥50%. |
| 2D Drawing Engine (DRW2D) | Hardware vector rendering (lines, circles), bit blitting with rotation/stretching - accelerates GUI redraw operations by 8× vs. CPU-only rendering. |
| Event Link Controller (ELC) | 83 internal event signals routed without CPU intervention - enables deterministic timer-triggered ADC sampling, PWM dead-time insertion, or CAN message transmission. |
| SD Host/Slave Interface | Single controller supporting SD memory, SDIO, and MMC cards in 1-/4-bit modes - simplifies removable media integration for data logging and field firmware updates. |
Applications
| Industrial HMI Terminal | Smart Gateway Controller |
|---|---|
Use Scenario: Touch-enabled operator interface for PLC-controlled machinery with local alarm logging and remote diagnostics via Ethernet. IC Role / Device Role / Timing Role: Main application processor executing RTOS, driving 4.3″–7″ TFT-LCD via GLCDC+DRW2D, managing CAN bus to field devices, and serving web pages over HTTP/HTTPS. Use Value: Integrated Ethernet MAC + dual CAN + hardware crypto eliminates external PHY, CAN transceivers, and security co-processors - reducing BOM cost by $2.10 and PCB area by 180 mm². |
Use Scenario: Protocol translator bridging Modbus RTU (RS485) field sensors to cloud MQTT over Ethernet/Wi-Fi (via external module). IC Role / Device Role / Timing Role: Central protocol stack executor with dual CAN for legacy vehicle bus integration, SDHI for offline log storage, and TSIP for TLS 1.2 session keys. Use Value: Dual-bank flash enables A/B firmware updates during runtime; 640 KB SRAM buffers multi-protocol packet translation without external PSRAM - cutting latency by 32 µs per packet. |
| Secure Edge Node | Networked Energy Meter |
Use Scenario: Tamper-resistant electricity meter with encrypted consumption reporting, anti-tampering detection, and OTA firmware validation. IC Role / Device Role / Timing Role: Security-critical controller using TSIP for AES-GCM encryption of meter data, MPU to isolate metering firmware from comms stack, and IWDT with window function for fail-safe reset. Use Value: On-chip AES + TSIP + MPU satisfies IEC 62056-21 and UL 2900-1 security requirements - avoids costly external secure element certification and reduces audit scope by 70%. |
Use Scenario: DIN-rail mounted energy monitor aggregating current/voltage readings from CT sensors, calculating kWh/kVAR, and transmitting via Ethernet to SCADA. IC Role / Device Role / Timing Role: Real-time data acquisition hub with dual 12-bit ADC units (21-channel unit 1 for sensor inputs), RTC with battery backup, and Ethernet MAC for time-synchronized reporting. Use Value: Simultaneous sampling across 12+ analog channels with ELC-triggered conversion ensures phase-accurate power calculations; integrated RTC eliminates external timekeeping IC. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F565NEDDFP#30 | Same RX65N family, 2 MB flash, 176-pin LQFP (PLQP0176KB-A footprint compatible but different mounting) | LQFP variant lacks GLCDC/DRW2D; targets non-display control applications with higher flash headroom | Select when display capability is unnecessary and through-hole assembly is preferred over BGA reflow. |
| R5F566TEADFP#30 | RX66T group, 160 MHz CPU, 1 MB flash, integrated encoder interface, no Ethernet MAC or GLCDC | Optimized for motor control with 3-phase PWM timers; lacks networking and graphics peripherals | Select for servo/inverter applications where real-time PWM timing dominates over connectivity and UI features. |
Compared with R5F5651EDGBG#20, R5F565NEDDFP#30 offers identical peripheral set in LQFP packaging but trades graphics acceleration for larger flash, while R5F566TEADFP#30 shifts focus to motor control precision at the expense of Ethernet and LCD support - making R5F5651EDGBG#20 uniquely balanced for connected HMI edge nodes.
Availability
R5F5651EDGBG#20 is available at Aetrix Electronics and suitable for industrial HMI terminals, smart gateways, secure edge nodes, and networked energy meters requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant manufacturing.
Supply support for R5F5651EDGBG#20 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a Japanese semiconductor manufacturer specializing in microcontrollers, analog, and power management ICs for industrial, automotive, and infrastructure markets.
The RX65N/RX651 Group targets industrial IoT edge devices requiring rich connectivity (Ethernet/CAN/SD), real-time graphics (GLCDC/DRW2D), and hardware security (TSIP/AES) - designed specifically for HMI, gateway, and secure metering applications.
FAQ
What is the maximum operating frequency and core type of the R5F5651EDGBG#20?
The R5F5651EDGBG#20 operates at a maximum frequency of 120 MHz using the 32-bit RXv2 CPU core. This core delivers 240 DMIPS performance and includes a single-precision IEEE-754 floating-point unit, two multiply-and-accumulate units, and a 5-stage pipeline - enabling deterministic real-time execution for industrial control and protocol stacks. The R5F5651EDGBG#20 achieves this performance with no wait states on its 640 KB SRAM.
Does the R5F5651EDGBG#20 support Ethernet and CAN interfaces?
Yes, the R5F5651EDGBG#20 integrates a full-featured Ethernet MAC supporting both MII and RMII interfaces at 10/100 Mbps, along with two independent CAN 2.0B controllers compliant with ISO 11898-1 - each supporting 32 mailboxes. These peripherals operate independently with dedicated DMA channels (EDMACa for Ethernet, DMACAa for CAN), allowing concurrent high-bandwidth communication without CPU intervention. The R5F5651EDGBG#20 requires only an external PHY for Ethernet and standard CAN transceivers.
What graphics and display capabilities does the R5F5651EDGBG#20 provide?
The R5F5651EDGBG#20 includes a dedicated Graphic-LCD Controller (GLCDC) supporting RGB565/RGB888 formats, three overlay planes (background, graphic 1, graphic 2), and resolutions up to XGA (1024×768). It also integrates a 2D Drawing Engine (DRW2D) that accelerates vector rendering, bit blitting, rotation, and stretching - offloading GUI operations from the CPU. Together, these allow the R5F5651EDGBG#20 to drive color TFT displays directly without external frame buffer memory or GPU.
How does the R5F5651EDGBG#20 handle security-critical functions like encryption and tamper protection?
The R5F5651EDGBG#20 incorporates Trusted Secure IP (TSIP) hardware that accelerates AES-128/192/256 encryption, key wrapping, and random number generation. It also features a Memory Protection Unit (MPU) with eight configurable regions, register write protection, and an Independent Watchdog Timer (IWDT) with window function - collectively satisfying IEC 60730 Class B requirements. These features enable secure boot, encrypted firmware storage, and runtime integrity checks within the R5F5651EDGBG#20 itself, eliminating reliance on external secure elements.
What is the package type and pin count of the R5F5651EDGBG#20?
The R5F5651EDGBG#20 uses the PLQP0176KB-A package: a 176-pin Low-Profile Fine-Pitch Ball Grid Array with 24 mm × 24 mm body size and 0.5 mm ball pitch. This package provides 136 general-purpose I/O pins with 5-V tolerance, open-drain capability, and programmable pull-up resistors - optimized for high-density industrial PCB layouts requiring robust thermal performance and signal integrity. The R5F5651EDGBG#20's pinout is documented in Renesas R01DS0276EJ0240 Section 5.1.
R5F5651EDGBG#20 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 176-LFBGA
- Series:
- RX651
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv2
- Core Size:
- 32-Bit
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, QSPI, SCI, SPI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 136
- Program Memory Size:
- 2MB (2M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 640K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 29x12b; D/A 2x12b
- Oscillator Type:
- External
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F5651EDGBG#20 FAQ
1.How can I place an order for R5F5651EDGBG#20 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F5651EDGBG#20 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F5651EDGBG#20 reliable?
The price and inventory of R5F5651EDGBG#20 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F5651EDGBG#20 is usually 5 days.
3.What payment methods are accepted for R5F5651EDGBG#20?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F5651EDGBG#20 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F5651EDGBG#20?
R5F5651EDGBG#20 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F5651EDGBG#20 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F5651EDGBG#20?
For technical support, including R5F5651EDGBG#20 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F5651EDGBG#20 requirements.
6.How does Aetrix verify that R5F5651EDGBG#20 is sourced from the original manufacturer or authorized distributors?
All R5F5651EDGBG#20 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F5651EDGBG#20 meets industry standards.
7.What is the process for return or replacement of R5F5651EDGBG#20?
All R5F5651EDGBG#20 units undergo pre-shipment inspection (PSI). If there is an issue with R5F5651EDGBG#20, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F5651EDGBG#20 part is unused and in its original packaging.
Return procedure for R5F5651EDGBG#20:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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