Renesas R5F5651EHGFM#10
- Part No.:
- R5F5651EHGFM#10
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 64-LQFP
- Datasheet:
-
R5F5651EHGFM#10.pdf
- Description:
- IC MCU 32BIT 2MB FLASH 64LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:1,358
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
R5F5651EHGFM#10 from Renesas is a 120-MHz 32-bit RXv2 microcontroller with integrated FPU, 240 DMIPS performance, 2 MB on-chip code flash (dual-bank), 640 KB SRAM, Ethernet MAC, CAN 2.0B, SD host/slave, QSPI, and hardware AES-128/192/256 encryption - designed for industrial HMI, networked gateways, and secure IoT edge nodes requiring real-time control and connectivity.
For engineers reviewing the R5F5651EHGFM#10 datasheet, R5F5651EHGFM#10 pinout, R5F5651EHGFM#10 application, or R5F5651EHGFM#10 equivalent, this MCU delivers deterministic real-time execution, IEC 60730-compliant safety features, dual-bank flash for safe firmware updates, and integrated peripherals including GLCDC + DRW2D for embedded graphics - critical for BOM-stable, long-lifecycle industrial designs.
Technical Context
The R5F5651EHGFM#10 implements the RXv2 CPU core with Harvard architecture, 5-stage pipeline, and variable-length instructions enabling ultra-compact code density. It integrates a single-precision IEEE-754 FPU, two MAC units, and a 32-bit multiplier with one-cycle execution - supporting high-accuracy motor control and sensor fusion algorithms.
Its clock system combines external crystal support (8–24 MHz), internal PLL, and multiple on-chip oscillators (LOCO, HOCO, IWDT-dedicated) to drive independent peripheral clocks: PCLKA up to 120 MHz (for ETHERC, GLCDC, DRW2D), PCLKB up to 60 MHz (for timers, ADC, UART), and dedicated ADCLKs for dual 12-bit S12AD units - enabling precise timing isolation across mixed-signal subsystems.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit CISC core with 5-stage pipeline, 240 DMIPS @ 120 MHz - enables deterministic real-time task scheduling in RTOS environments. |
| Flash Memory | 2 MB code flash with dual-bank structure - supports background programming and zero-downtime firmware updates via bank swap. |
| SRAM | 640 KB on-chip SRAM (256 KB main + 384 KB expansion), no wait states @ 120 MHz - eliminates external RAM for complex GUI or protocol stack buffering. |
| Analog Peripherals | Dual 12-bit A/D converters (8 + 21 channels), 2-channel 12-bit D/A, on-die temperature sensor (±1°C) - enables full-sensor-node integration without external signal conditioning. |
| Connectivity | Ethernet MAC (10/100 Mbps MII/RMII), 2-channel CAN 2.0B (32 mailboxes/channel), USB 2.0 FS host/function/OTG, SDHI/SDSI/MMCIF - consolidates wired industrial comms into single chip. |
| Security & Safety | AES-128/192/256, TSIP, MPU (8 regions), CRC calculator (8/32-bit), IEC 60730 self-test functions - meets SIL-2 functional safety requirements for industrial controllers. |
| Package | PLQP0176KB-A, 176-pin LQFP, 24 × 24 mm, 0.5-mm pitch - provides 136 general-purpose I/O pins with 5-V tolerance and configurable drive strength. |
Pinout & Package
PLQP0176KB-A: 176-pin Low-profile Quad Flat Package, 24 mm × 24 mm, 0.5 mm pitch, RoHS-compliant, lead-free, moisture sensitivity level 3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Power supply inputs | Separate digital (VCC) and analog (AVCC0/AVCC1) rails enable noise isolation for precision ADC/DAC operation. |
| RES# | Active-low reset input | Asynchronous hardware reset with internal pull-up; initiates full system reset including peripheral registers and memory controllers. |
| XTAL / EXTAL | Main crystal oscillator interface | Supports 8–24 MHz external crystal for high-accuracy system clock; paired with on-chip PLL for stable 120 MHz core frequency. |
| MD0 / MD1 | Mode setting pins | Configure boot mode (SCI/USB/FINE) and operating mode (single-chip/on-chip ROM enabled/disabled) at power-on reset. |
| ETXD0–ETXD3 / ETXCK / ERXD0–ERXD3 / ERXCK | Ethernet PHY interface | MII-mode signals for direct connection to external Ethernet PHY; RMII mode uses subset (ETXD0/ETXCK/ERXD0/ERXDV/ERXER). |
| TXD0 / RXD0 | SCI0 asynchronous serial interface | Full-duplex UART channel for debug console, configuration interface, or host communication - supports baud rates up to 15 Mbps with fractional divider. |
Key Features
| Feature | Design Value |
|---|---|
| Trusted Secure IP (TSIP) | Hardware-accelerated AES encryption/decryption with key wrapping and secure key storage - prevents firmware extraction and enables secure OTA updates. |
| Graphic-LCD Controller (GLCDC) | Supports 3-layer overlay (background + 2 graphics planes), 32-/16-bpp formats, and CLUT-based color mapping - drives industrial LCD panels up to WXGA without external GPU. |
| 2D Drawing Engine (DRW2D) | Hardware-accelerated vector drawing (lines, circles, triangles) and bit blitting with rotation/stretching - reduces CPU load for dynamic HMI rendering by >70% vs software-only. |
| Event Link Controller (ELC) | 83 internal event sources routed to 16 peripheral modules without CPU intervention - enables deterministic timer-triggered ADC sampling or PWM synchronization. |
| IEC 60730 Compliance Support | Integrated oscillation-stop detection, CRC calculator, IWDT windowing, A/D self-diagnostic, and register write protection - satisfies Class B safety requirements out-of-box. |
Applications
| Industrial HMI Panel | Smart Gateway Controller |
|---|---|
Use Scenario: Embedded display controller for factory-floor HMIs with touch, button, and LED feedback. IC Role / Device Role / Timing Role: Main application processor running FreeRTOS, driving GLCDC + DRW2D for real-time UI rendering, and managing CAN/Ethernet fieldbus bridging. Use Value: On-chip 640 KB SRAM buffers frame data; dual-bank flash enables seamless firmware upgrades during operation without UI freeze. | Use Scenario: Protocol translation gateway connecting Modbus RTU devices to cloud via Ethernet/Wi-Fi (via external transceiver). IC Role / Device Role / Timing Role: Central protocol stack executor with simultaneous CAN 2.0B, Ethernet MAC, and SDHI for local logging - all managed via ELC-triggered DMA transfers. Use Value: Hardware CRC and AES acceleration offload security processing; 136 GPIOs support isolated I/O expansion for relay/LED/status monitoring. |
| Secure IoT Edge Node | Networked Motor Drive Controller |
Use Scenario: Field-deployed sensor aggregator with encrypted telemetry upload and remote firmware update capability. IC Role / Device Role / Timing Role: Trusted execution environment using TSIP and MPU to isolate secure boot, crypto operations, and sensor data handling from application tasks. Use Value: Dual 12-bit ADCs sample current/voltage sensors at 2.1 MSPS aggregate rate; AES-256 encrypts payloads before transmission over Ethernet. | Use Scenario: Closed-loop servo drive with position feedback, current sensing, and EtherCAT slave interface (via external PHY). IC Role / Device Role / Timing Role: Real-time motion controller executing FOC algorithms using RXv2 FPU and MTU3 complementary PWM outputs with dead-time compensation. Use Value: 120 MHz core + 240 DMIPS delivers sub-10 µs current loop execution; hardware PWM sync ensures <100 ns phase alignment across 3-phase outputs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F565NEHGFM#10 | Same RX65N family, identical 176-pin PLQP package, but with 1.5 MB flash and 256 KB SRAM (no expansion RAM). | Suitable for cost-sensitive designs where GUI complexity or protocol stack memory footprint is lower. | Select when firmware size ≤ 1.5 MB and frame buffer requirements fit within 256 KB SRAM. |
| R7FA6M2AF3CFP#AA0 | RX72M-based, 240 MHz, 1 MB flash, 384 KB SRAM, integrated EtherCAT slave controller - no GLCDC/DRW2D. | Targeted at motion control systems requiring hard real-time EtherCAT compliance, not graphics-intensive HMIs. | Choose for EtherCAT master/slave applications where deterministic 1 µs cycle times outweigh graphics needs. |
Compared with R5F565NEHGFM#10, the R5F5651EHGFM#10 offers 500 KB more flash and 384 KB additional SRAM for larger firmware images and richer GUI assets; versus R7FA6M2AF3CFP#AA0, it trades EtherCAT timing precision for integrated graphics acceleration and broader peripheral flexibility in non-EtherCAT industrial networks.
Availability
R5F5651EHGFM#10 is available at Aetrix Electronics and suitable for industrial HMI development, smart gateway deployment, and secure IoT edge node production requiring stable component supply across 10+ year product lifecycles.
Supply support for R5F5651EHGFM#10 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader delivering trusted embedded solutions for automotive, industrial, infrastructure, and IoT markets - headquartered in Tokyo, Japan.
The RX65N Group, which includes the R5F5651EHGFM#10, was engineered for industrial automation and human-machine interface applications demanding high reliability, rich connectivity, and integrated graphics acceleration - with focus on long-term availability and functional safety certification readiness.
FAQ
What is the maximum operating frequency and core architecture of the R5F5651EHGFM#10?
The R5F5651EHGFM#10 operates at a maximum frequency of 120 MHz using the 32-bit RXv2 CPU core with Harvard architecture, 5-stage pipeline, and variable-length instruction set. It achieves 240 DMIPS performance and includes a single-precision IEEE-754 floating-point unit - making the R5F5651EHGFM#10 suitable for real-time control algorithms requiring high computational throughput and deterministic timing.
Does the R5F5651EHGFM#10 support dual-bank flash for firmware updates?
Yes, the R5F5651EHGFM#10 includes 2 MB of on-chip code flash memory organized in a dual-bank structure. This allows background programming of one bank while executing code from the other, enabling safe, zero-downtime firmware updates - a critical capability for the R5F5651EHGFM#10 in always-on industrial gateways and HMIs where system availability must be maintained during field upgrades.
What graphics capabilities does the R5F5651EHGFM#10 provide?
The R5F5651EHGFM#10 integrates both a Graphic-LCD Controller (GLCDC) supporting 3-layer overlay and a hardware 2D Drawing Engine (DRW2D) for vector and bitmap acceleration. These peripherals enable direct driving of industrial LCD panels up to WXGA resolution and reduce CPU load for dynamic UI rendering - making the R5F5651EHGFM#10 ideal for feature-rich HMIs without external graphics processors.
How many communication interfaces does the R5F5651EHGFM#10 include?
The R5F5651EHGFM#10 integrates Ethernet MAC (10/100 Mbps), 2-channel CAN 2.0B (32 mailboxes per channel), USB 2.0 FS host/function/OTG, SD host/slave, MMCIF, QSPI, 3-channel RSPI, 13-channel SCI, 3-channel I2C, and parallel camera interface - providing comprehensive wired connectivity for industrial networking, data acquisition, and multimedia applications in the R5F5651EHGFM#10.
What safety and security features are built into the R5F5651EHGFM#10?
The R5F5651EHGFM#10 includes a Memory Protection Unit (MPU), Trusted Secure IP (TSIP) with AES-128/192/256, CRC calculator, register write protection, and IEC 60730-compliant self-test functions (oscillation stop detection, A/D diagnostic, IWDT windowing). These features collectively support SIL-2 functional safety and secure boot requirements - essential for certified deployments of the R5F5651EHGFM#10 in industrial control systems.
R5F5651EHGFM#10 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 64-LQFP
- Series:
- RX651
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv2
- Core Size:
- 32-Bit
- Speed:
- 120MHz
- Connectivity:
- I2C, LINbus, MMC/SD, QSPI, SCI, SPI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 42
- Program Memory Size:
- 2MB (2M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 640K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 10x12b; D/A 1x12b
- Oscillator Type:
- External
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F5651EHGFM#10 FAQ
1.How can I place an order for R5F5651EHGFM#10 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F5651EHGFM#10 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F5651EHGFM#10 reliable?
The price and inventory of R5F5651EHGFM#10 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F5651EHGFM#10 is usually 5 days.
3.What payment methods are accepted for R5F5651EHGFM#10?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F5651EHGFM#10 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F5651EHGFM#10?
R5F5651EHGFM#10 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F5651EHGFM#10 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F5651EHGFM#10?
For technical support, including R5F5651EHGFM#10 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F5651EHGFM#10 requirements.
6.How does Aetrix verify that R5F5651EHGFM#10 is sourced from the original manufacturer or authorized distributors?
All R5F5651EHGFM#10 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F5651EHGFM#10 meets industry standards.
7.What is the process for return or replacement of R5F5651EHGFM#10?
All R5F5651EHGFM#10 units undergo pre-shipment inspection (PSI). If there is an issue with R5F5651EHGFM#10, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F5651EHGFM#10 part is unused and in its original packaging.
Return procedure for R5F5651EHGFM#10:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R5F5651EHGFM#10 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

