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Renesas R5F5651EHGLC#20
- Part No.:
- R5F5651EHGLC#20
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 176-LFBGA
- Datasheet:
-
R5F5651EHGLC#20.pdf
- Description:
- IC MCU 32BIT 2MB FLASH 176LFBGA
- Quantity:
- Payment:
- Shipping:
Inventory:319
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Product details
Overview
R5F5651EHGLC#20 from Renesas is a 32-bit RXv2 microcontroller with 120 MHz CPU frequency, 240 DMIPS performance, single-precision IEEE-754 FPU, 2 MB on-chip code flash memory, and 640 KB SRAM. It integrates Ethernet MAC, dual CAN channels, SD host/slave interfaces, QSPI, GLCDC, DRW2D, and hardware AES/TSIP encryption - deployed in industrial HMI, networked gateway controllers, and secure IoT edge nodes.
For engineers reviewing the R5F5651EHGLC#20 datasheet, R5F5651EHGLC#20 pinout, R5F5651EHGLC#20 application, or R5F5651EHGLC#20 equivalent, key selection criteria include its 176-pin LFBGA package (PLQP0176KB-A), -40°C to +85°C operating range, dual-bank flash for safe firmware updates, 12-bit dual A/D converters with self-diagnostic capability, and integrated Ethernet PHY support via external transceiver.
Technical Context
The R5F5651EHGLC#20 implements the RXv2 CISC Harvard architecture with 5-stage pipeline, variable-length instructions, and MPU-based memory protection. It supports little-endian or big-endian data arrangement and executes 32×32→64-bit multiply and 32/32→32-bit divide in one or two cycles respectively.
Clocking is managed via PLL (up to 120 MHz ICLK), multiple on-chip oscillators (LOCO/HOCO/IWDT), and independent peripheral clock domains (PCLKA up to 120 MHz for ETHERC/DRW2D, PCLKB up to 60 MHz for timers/A/D). Reset sources include POR, LVD (three levels), deep software standby, and independent watchdog timer with window function.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit CISC with 5-stage pipeline, 240 DMIPS @ 120 MHz |
| Flash Memory | 2 MB code flash with dual-bank structure enabling background programming and safe bank switching during runtime |
| SRAM | 640 KB total: 256 KB main RAM + 384 KB expansion RAM, all zero-wait-state at 120 MHz |
| A/D Converter | Dual 12-bit S12AD units: Unit 0 (8 ch), Unit 1 (21 ch); 0.48 µs conversion time; self-diagnostic & disconnection detection |
| Communication | Ethernet MAC (10/100 Mbps), 2× CAN (ISO 11898-1), 3× RSPI, 1× QSPI, 3× I²C (1 Mbps), 13× SCI, SDHI/SDSI/MMCIF |
| Security | AES-128/192/256, Trusted Secure IP (TSIP), MPU (8 regions), register write protection, CRC calculator (8/32-bit) |
| Package | PLQP0176KB-A: 176-pin LFBGA, 24 × 24 mm, 0.5 mm pitch, -40°C to +85°C (D-version) |
Pinout & Package
Package: PLQP0176KB-A - 176-pin Low-Profile Fine-Pitch Ball Grid Array (LFBGA), 24 mm × 24 mm, 0.5 mm ball pitch, RoHS-compliant, lead-free, moisture sensitivity level 3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Power supply inputs | Core (VCC), analog unit 0 (AVCC0), analog unit 1 (AVCC1) - each require separate 2.7–3.6 V decoupling |
| VBATT | Battery backup supply | Provides power to RTC during main supply loss; enables calendar/clock retention in deep software standby |
| RES# | Active-low reset input | Asynchronous hardware reset; low pulse ≥ 100 ns initiates full system reset sequence |
| XTAL / EXTAL | Main crystal oscillator interface | Supports 8–24 MHz external crystal/resonator; required for high-accuracy timing and Ethernet PHY synchronization |
| MD0 / MD1 | Mode setting pins | Determine boot mode (SCI/USB/FINE) and operating mode (single-chip/ROM-enabled extended) at power-on reset |
| ETXD0–7 / ERXD0–7 / ETX_EN / ERX_DV | Ethernet MII interface signals | Direct connection to external PHY; supports 10/100 Mbps full/half-duplex per IEEE 802.3u; requires impedance-controlled PCB routing |
Key Features
| Feature | Design Value |
|---|---|
| Trusted Secure IP (TSIP) | Hardware-accelerated AES and secure key management enabling certified IEC 60730 Class B compliance without software overhead |
| Dual-bank flash memory | Enables seamless firmware updates: new image programmed in inactive bank while active bank continues execution |
| Graphic-LCD controller (GLCDC) | Supports 3-layer overlay (background + 2 graphics), 32/16 bpp formats, and direct frame buffer access - eliminates external display controller |
| 2D drawing engine (DRW2D) | Offloads CPU with hardware vector rendering (lines, circles), bit blitting (rotate/scale/copy), and CLUT-based color conversion |
| Event Link Controller (ELC) | 83 internal event signals routed without CPU intervention - e.g., TPU output triggers A/D conversion or GPIO toggle |
| IEC 60730 safety functions | Includes oscillation-stop detection, CRC calculation, IWDT windowing, A/D self-test, and register write protection for functional safety certification |
Applications
| Industrial HMI Panel | Secure Network Gateway |
|---|---|
Use Scenario: Touch-enabled operator interface for PLC-controlled machinery with real-time status visualization and alarm logging. IC Role / Device Role / Timing Role: Main application processor running RTOS, driving 480×272 LCD via GLCDC, capturing touch via SCI-based controller, and communicating over CAN/Ethernet. Use Value: Integrated DRW2D accelerates UI rendering; dual-bank flash allows remote firmware patching without downtime; TSIP secures OTA update integrity. |
Use Scenario: Edge gateway aggregating Modbus RTU sensors and forwarding data to cloud via TLS-secured Ethernet/Wi-Fi bridge. IC Role / Device Role / Timing Role: Protocol translator and security enforcer - terminates fieldbus, performs AES-encrypted TLS handshake, and manages secure boot chain. Use Value: Hardware AES/TSIP reduces TLS handshake latency by >60% vs. software-only; Ethernet MAC + SDHI enables local log storage on encrypted SD card. |
| Medical Data Logger | Smart Energy Meter |
Use Scenario: Battery-backed portable device recording ECG waveforms, ambient temperature, and patient ID via NFC/USB. IC Role / Device Role / Timing Role: Sensor fusion hub - samples analog front-end via dual S12AD, timestamps data using RTC with battery backup, stores to SD card. Use Value: Standby RAM (8 KB) retains critical buffers during sleep; A/D self-diagnostic ensures clinical-grade signal integrity; USB FS host loads config via flash drive. |
Use Scenario: DIN-rail mounted meter with pulse counting, tariff switching, tamper detection, and DLMS/COSEM over PRIME PLC or RF mesh. IC Role / Device Role / Timing Role: Metrology co-processor and communications manager - reads metrology IC via SPI, runs DLMS stack, signs firmware updates with TSIP. Use Value: Dual CAN channels enable redundant communication paths; 120-kHz IWDT with windowing meets IEC 62056-21 fault response requirements; CRC calculator validates meter registers. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F565NEDFP#30 | Same RX65N family, 144-pin LQFP package (PLQP0144KA-B), 1.5 MB flash, 256 KB SRAM, no Ethernet MAC | Lacks integrated Ethernet MAC and GLCDC; suited for cost-sensitive control-only nodes without display or wired LAN | Select when board space permits LQFP, Ethernet is handled externally, and display is not required - reduces BOM cost by ~18% |
| R5F566TEHGLC#20 | RX66T group, same 176-pin LFBGA, 2 MB flash, but optimized for motor control: 3× MTU3 units, 3-phase PWM with dead-time control, no SDHI/GLCDC | Targets servo drives and inverters; replaces general-purpose peripherals with advanced timer/PWM resources for FOC algorithms | Choose for high-performance motor control where Ethernet and graphics are secondary - gains 3× more PWM channels and faster ADC trigger latency |
Compared with R5F5651EHGLC#20, the R5F565NEDFP#30 trades Ethernet and display capability for lower cost and simpler layout, while the R5F566TEHGLC#20 shifts focus from connectivity and UI to deterministic motor control - neither is pin-compatible, but both share toolchain and peripheral register compatibility within Renesas' e2 studio ecosystem.
Availability
R5F5651EHGLC#20 is available at Aetrix Electronics and suitable for industrial HMI, secure gateways, medical data loggers, and smart energy meters requiring stable component supply across multi-year production cycles.
Supply support for R5F5651EHGLC#20 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and enterprise applications.
The R5F5651EHGLC#20 belongs to the RX65N Group - designed for secure, connected industrial devices requiring rich peripheral integration, functional safety support (IEC 60730), and real-time graphics capability without external controllers.
FAQ
What is the maximum operating frequency and core architecture of the R5F5651EHGLC#20?
The R5F5651EHGLC#20 operates at a maximum frequency of 120 MHz using the 32-bit RXv2 CPU core. This core features a 5-stage pipeline, Harvard architecture, variable-length instructions, and delivers 240 DMIPS performance. It supports single-precision IEEE-754 floating-point operations, 32×32-bit multiplication in one cycle, and includes a memory protection unit (MPU) for secure memory partitioning - all confirmed in Renesas document R01DS0276EJ0240.
Does the R5F5651EHGLC#20 support Ethernet connectivity, and what interface does it use?
Yes, the R5F5651EHGLC#20 integrates a full-featured Ethernet MAC compliant with IEEE 802.3, supporting 10/100 Mbps in full- and half-duplex modes. It uses the MII interface (14 signals: ETXD0–7, ERXD0–7, ETX_EN, ERX_DV) and requires an external PHY. The EDMACa DMA controller offloads packet handling, and wake-on-LAN (Magic Packet™) detection is supported - details are specified on page 7 of R01DS0276EJ0240.
What are the flash and RAM configurations of the R5F5651EHGLC#20?
The R5F5651EHGLC#20 includes 2 MB of on-chip code flash memory with dual-bank structure for background programming and safe bank switching, plus 32 KB of data flash rated for 100,000 erase/write cycles. Its RAM consists of 640 KB total: 256 KB main SRAM and 384 KB expansion SRAM - all accessible with zero wait states at 120 MHz - as defined in Table 1.1 of R01DS0276EJ0240.
How many A/D converter channels does the R5F5651EHGLC#20 provide, and what diagnostic features are included?
The R5F5651EHGLC#20 integrates two independent 12-bit A/D converter units: S12AD unit 0 with 8 channels and unit 1 with 21 channels. Both support 8/10/12-bit resolution, 0.48 µs conversion time, and include self-diagnostic functions that internally generate reference voltages (e.g., VREFL0, VREFH0 × 1/2) to verify analog path integrity - a key requirement for IEC 60730 Class B certification.
What security features are implemented in hardware on the R5F5651EHGLC#20?
The R5F5651EHGLC#20 includes hardware-accelerated AES-128/192/256 encryption, Trusted Secure IP (TSIP) for key management and secure boot, an 8-region memory protection unit (MPU), register write protection to prevent accidental overwrite, and a configurable CRC calculator supporting 8- and 32-bit polynomials - all documented in Sections 1.1 and 2.12 of R01DS0276EJ0240 for functional safety and secure firmware deployment.
R5F5651EHGLC#20 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 176-LFBGA
- Series:
- RX651
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- RXv2
- Core Size:
- 32-Bit
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, QSPI, SCI, SPI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 136
- Program Memory Size:
- 2MB (2M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 640K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 29x12b; D/A 2x12b
- Oscillator Type:
- External
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F5651EHGLC#20 FAQ
1.How can I place an order for R5F5651EHGLC#20 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F5651EHGLC#20 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F5651EHGLC#20 reliable?
The price and inventory of R5F5651EHGLC#20 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F5651EHGLC#20 is usually 5 days.
3.What payment methods are accepted for R5F5651EHGLC#20?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F5651EHGLC#20 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F5651EHGLC#20?
R5F5651EHGLC#20 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F5651EHGLC#20 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F5651EHGLC#20?
For technical support, including R5F5651EHGLC#20 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F5651EHGLC#20 requirements.
6.How does Aetrix verify that R5F5651EHGLC#20 is sourced from the original manufacturer or authorized distributors?
All R5F5651EHGLC#20 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F5651EHGLC#20 meets industry standards.
7.What is the process for return or replacement of R5F5651EHGLC#20?
All R5F5651EHGLC#20 units undergo pre-shipment inspection (PSI). If there is an issue with R5F5651EHGLC#20, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F5651EHGLC#20 part is unused and in its original packaging.
Return procedure for R5F5651EHGLC#20:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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