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Renesas R5F5651EHGLK#20
- Part No.:
- R5F5651EHGLK#20
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 145-TFLGA
- Datasheet:
-
R5F5651EHGLK#20.pdf
- Description:
- IC MCU 32BIT 2MB FLASH 145TFLGA
- Quantity:
- Payment:
- Shipping:
Inventory:416
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Product details
Overview
R5F5651EHGLK#20 from Renesas is a 32-bit RXv2 core MCU operating at up to 120 MHz (240 DMIPS), featuring 2 MB on-chip code flash, 640 KB SRAM, single-precision IEEE-754 FPU, Ethernet MAC, dual CAN channels, and hardware AES/TSIP encryption - deployed in industrial HMI, networked gateway, and secure IoT edge controllers.
For engineers reviewing the R5F5651EHGLK#20 datasheet, R5F5651EHGLK#20 pinout, R5F5651EHGLK#20 application, or R5F5651EHGLK#20 equivalent, key selection criteria include its 176-pin LFBGA package, dual-bank flash for safe firmware updates, 12-bit dual A/D converters with self-diagnostic capability, integrated GLCDC + DRW2D for embedded graphics, and IEC60730-compliant safety features including CRC, IWDT, and register write protection.
Technical Context
The R5F5651EHGLK#20 implements the RXv2 CISC Harvard architecture with 5-stage pipeline, variable-length instructions, and MPU-enforced memory protection. It integrates dual-clock domain operation: ICLK up to 120 MHz for CPU/core logic, PCLKA up to 120 MHz for high-speed peripherals (ETHERC, EDMAC, AES, GLCDC), and PCLKB up to 60 MHz for timers, ADCs, and communication interfaces.
Its peripheral subsystem includes dedicated hardware accelerators: EXDMAC (2-channel), DMACAa (8-channel), DTCb (1-channel), and event-link controller (ELC) enabling CPU-free inter-module triggering. Clock sources include external crystal (8–24 MHz), internal HOCO (16/18/20 MHz), LOCO (240 kHz), and IWDT-dedicated oscillator (120 kHz).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit CISC Harvard, 120 MHz max, 240 DMIPS, IEEE-754 FPU, 72-bit accumulators |
| Memory | 2 MB dual-bank code flash (no-wait ≤50 MHz), 32 KB data flash (100k erase cycles), 640 KB SRAM (no-wait @120 MHz) |
| Analog Peripherals | Two 12-bit S12AD units (8 + 21 ch), 2× R12DA DACs, on-die temperature sensor (±1°C) |
| Connectivity | Ethernet MAC + RMII/MII, 2× CAN (ISO11898-1, 32 mailboxes/channel), 13× SCI, 3× RSPI, QSPI, 3× RIIC (1 Mbps), SDHI/SDSI/MMCIF |
| Graphics & Timing | GLCDC + DRW2D engine, 176-pin LFBGA (13 × 13 mm, 0.8 mm pitch), –40°C to +105°C (G-version) |
| Security & Safety | AES-128/192/256, TSIP, MPU (8 regions), CRCA, IWDT with window function, register write protection, IEC60730 support |
Pinout & Package
Package: PLBG0176GA-A, 176-pin LFBGA, 13 × 13 mm, 0.8 mm pitch, RoHS compliant, moisture sensitivity level 3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Power supply inputs | Separate digital/analog domains; AVCC0/AVCC1 power analog peripherals and ADC/DAC reference |
| RES# | Active-low reset input | Asynchronous hardware reset; triggers POR/LVD-initiated internal reset sequence |
| CLKIN / CLKOUT | External crystal interface | Supports 8–24 MHz crystal; enables PLL-based 120 MHz system clock generation |
| ETH_MDC / ETH_MDIO | MDIO management interface | IEEE 802.3-compliant PHY configuration and status access for integrated Ethernet MAC |
| TXD0 / RXD0 | SCI0 asynchronous serial I/O | Full-duplex UART interface; supports baud rates up to 15 Mbps with programmable sampling |
| MTIOC0A / MTIOC0B | MTU3 channel 0 PWM output | Complementary PWM outputs with programmable dead time; used for motor control or power stage timing |
Key Features
| Feature | Design Value |
|---|---|
| Dual-bank flash architecture | Enables background programming and seamless bank switching during runtime for OTA firmware updates without interruption |
| Integrated GLCDC + DRW2D | Hardware-accelerated 2D rendering and LCD panel control - eliminates external GPU need in HMI designs |
| IEC60730-compliant safety suite | Includes oscillation-stop detection, CRC calculator (8/32-bit), IWDT with windowing, and self-test for A/D converter |
| Event Link Controller (ELC) | 83 internal event signals routed without CPU intervention - reduces latency and ISR overhead in real-time control loops |
| Secure boot & Trusted Memory (TM) | Code flash region protected against read-out; only CPU instruction fetch allowed - prevents firmware reverse engineering |
Applications
| Industrial HMI Controller | Secure Network Gateway |
|---|---|
Use Scenario: Embedded touch-panel display with local logic, Ethernet backhaul, and USB host for field service tools. IC Role / Device Role / Timing Role: Main application processor managing GLCDC, DRW2D, touch controller interface, and Ethernet MAC stack. Use Value: On-chip graphics engine and 640 KB SRAM eliminate external frame buffer; dual-bank flash enables safe field firmware patching. |
Use Scenario: Edge node aggregating CAN bus data from machinery and forwarding via Ethernet to cloud infrastructure. IC Role / Device Role / Timing Role: Protocol bridge with CAN-to-Ethernet translation, TLS offload via TSIP, and secure boot enforcement. Use Value: Dual CAN channels (64 mailboxes total) handle concurrent industrial networks; AES/TSIP accelerates encrypted MQTT/TLS sessions. |
| Smart Energy Meter | Medical Device Controller |
Use Scenario: DIN-rail mounted meter with RTC, tamper detection, SD card logging, and isolated RS485 communication. IC Role / Device Role / Timing Role: System-on-chip managing metrology ADC interface, RTC with battery backup, and secure data storage. Use Value: Standby RAM (8 KB) preserves state during brownout; IEC60730 features satisfy Class B functional safety requirements. |
Use Scenario: Portable diagnostic device requiring low-power operation, USB HID interface, and real-time sensor fusion. IC Role / Device Role / Timing Role: Real-time sensor hub with 12-bit dual A/D converters, temperature compensation, and USB 2.0 FS device mode. Use Value: 120 MHz FPU enables floating-point FFT for signal processing; 5-V tolerant I/O simplifies connection to legacy sensors. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F5651EHLFK#20 | Same RX651 Group die, but in 176-pin LFQFP (24 × 24 mm, 0.5 mm pitch); no LFBGA thermal pad; slightly lower thermal performance | Suitable for prototyping or cost-sensitive PCBs where fine-pitch BGA assembly is unavailable | Select when manual rework or standard SMT lines are required instead of BGA-reflow capability |
| R5F5661EHGLK#20 | RX661 Group successor: identical pinout, higher max frequency (160 MHz), enhanced TSIP-Lite, larger SRAM (1 MB), added CAN FD support | Drop-in upgrade path for future-proofing; requires updated BSP and validation for CAN FD timing margins | Choose for new designs targeting extended lifecycle, higher throughput, or CAN FD interoperability |
Compared with R5F5651EHGLK#20, the R5F5651EHLFK#20 offers identical functionality in a through-hole-friendly package but sacrifices thermal efficiency, while the R5F5661EHGLK#20 delivers measurable performance and security uplift with full pin compatibility - making it the preferred migration path for production scalability.
Availability
R5F5651EHGLK#20 is available at Aetrix Electronics and suitable for industrial HMI, secure network gateways, smart energy meters, and medical device controllers requiring stable component supply across extended product lifecycles.
Supply support for R5F5651EHGLK#20 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader headquartered in Tokyo, Japan, specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and enterprise markets.
The RX651 Group - including the R5F5651EHGLK#20 - was designed for high-integrity industrial edge applications demanding real-time responsiveness, graphical user interfaces, network connectivity, and functional safety compliance.
FAQ
What is the maximum operating frequency and core architecture of the R5F5651EHGLK#20?
The R5F5651EHGLK#20 operates at a maximum frequency of 120 MHz using the 32-bit RXv2 CPU core. This core implements a CISC Harvard architecture with a 5-stage pipeline, variable-length instructions, and single-cycle 32×32-bit multiplication. It delivers 240 DMIPS and includes a single-precision IEEE-754 floating-point unit, two multiply-accumulate units, and support for big- or little-endian data arrangement - all confirmed in the official R01DS0276EJ0240 datasheet.
Does the R5F5651EHGLK#20 support secure boot and cryptographic acceleration?
Yes, the R5F5651EHGLK#20 supports secure boot via its Trusted Memory (TM) function, which protects designated code flash regions from unauthorized read access. It also integrates hardware AES engines supporting 128-, 192-, and 256-bit keys, plus the Trusted Secure IP (TSIP) module for key management and secure cryptographic operations - all documented in Section 1.1 and Chapter 33 of the R01DS0276EJ0240 datasheet.
What are the package dimensions and thermal characteristics of the R5F5651EHGLK#20?
The R5F5651EHGLK#20 uses the PLBG0176GA-A package: a 176-pin LFBGA with 13 × 13 mm body size, 0.8 mm pitch, and exposed thermal pad. Its operating temperature range is –40°C to +105°C (G-version), and it supports four low-power modes including deep software standby with 8 KB battery-backed RAM - specifications verified in Tables 1.1 and 1.2 of the R01DS0276EJ0240 datasheet.
How many CAN channels and mailboxes does the R5F5651EHGLK#20 provide?
The R5F5651EHGLK#20 integrates two independent CAN modules compliant with ISO11898-1, each supporting up to 32 message mailboxes - totaling 64 configurable receive/transmit buffers. This enables concurrent handling of multiple CAN networks (e.g., drive train and diagnostics buses) without software arbitration overhead, as specified in Section 1.1 "Communication Function" of the R01DS0276EJ0240 datasheet.
Is the R5F5651EHGLK#20 pin-compatible with other members of the RX651 Group?
Yes, the R5F5651EHGLK#20 shares identical pinout and electrical characteristics with other 176-pin variants in the RX651 Group, including R5F5651EHLFK#20 (LFQFP) and R5F5651EHMLK#20 (LFBGA with different flash size). All share the same PLBG0176GA-A footprint, I/O voltage tolerance (5 V), and peripheral mapping - confirmed in Table 1.2 "Code Flash Memory Capacity and Comparison of Functions for Different Packages" of R01DS0276EJ0240.
R5F5651EHGLK#20 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 145-TFLGA
- Series:
- RX651
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- RXv2
- Core Size:
- 32-Bit Single-Core
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, QSPI, SCI, SPI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 111
- Program Memory Size:
- 2MB (2M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 640K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 29x12b; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F5651EHGLK#20 FAQ
1.How can I place an order for R5F5651EHGLK#20 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F5651EHGLK#20 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F5651EHGLK#20 reliable?
The price and inventory of R5F5651EHGLK#20 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F5651EHGLK#20 is usually 5 days.
3.What payment methods are accepted for R5F5651EHGLK#20?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F5651EHGLK#20 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F5651EHGLK#20?
R5F5651EHGLK#20 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F5651EHGLK#20 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F5651EHGLK#20?
For technical support, including R5F5651EHGLK#20 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F5651EHGLK#20 requirements.
6.How does Aetrix verify that R5F5651EHGLK#20 is sourced from the original manufacturer or authorized distributors?
All R5F5651EHGLK#20 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F5651EHGLK#20 meets industry standards.
7.What is the process for return or replacement of R5F5651EHGLK#20?
All R5F5651EHGLK#20 units undergo pre-shipment inspection (PSI). If there is an issue with R5F5651EHGLK#20, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F5651EHGLK#20 part is unused and in its original packaging.
Return procedure for R5F5651EHGLK#20:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R5F5651EHGLK#20 Tags
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