Renesas R5F565N4AGFB#10
- Part No.:
- R5F565N4AGFB#10
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 144-LQFP
- Datasheet:
-
R5F565N4AGFB#10.pdf
- Description:
- IC MCU 32BIT 512KB FLASH 144LQFP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
R5F565N4AGFB#10 from Renesas is a 32-bit RXv2 microcontroller with 120 MHz CPU frequency, 240 DMIPS performance, single-precision IEEE-754 FPU, 2 MB on-chip code flash memory, and 640 KB SRAM. It integrates Ethernet MAC, dual CAN channels (ISO 11898-1), SD host/slave interfaces, QSPI, GLCDC, DRW2D, and hardware AES encryption - targeting industrial HMI, networked gateways, and secure IoT edge controllers.
For engineers reviewing the R5F565N4AGFB#10 datasheet, R5F565N4AGFB#10 pinout, R5F565N4AGFB#10 application, or R5F565N4AGFB#10 equivalent, key selection criteria include its 176-pin LFBGA package (PLQP0176KB-A), 120 MHz real-time deterministic execution, dual-bank flash for safe firmware updates, integrated Ethernet PHY support, and IEC 60730-compliant safety features including CRC, IWDT, and register write protection.
Technical Context
The R5F565N4AGFB#10 implements the RXv2 CPU core with CISC Harvard architecture, 5-stage pipeline, and variable-length instructions enabling ultra-compact code density. It supports little-endian or big-endian data arrangement and includes two 72-bit accumulators, a 32×32→64-bit multiplier, and a 32/32→32-bit divider with one- and two-cycle latency respectively.
Its clock system combines external crystal (8–24 MHz) and internal oscillators (LOCO at 240 kHz, HOCO at 16/18/20 MHz), with independent PLL-based domain clocks: ICLK up to 120 MHz for CPU, PCLKA up to 120 MHz for high-speed peripherals (ETHERC, GLCDC, DRW2D), and PCLKB up to 60 MHz for timers and ADCs - enabling precise timing partitioning across subsystems.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit CISC core with 5-stage pipeline, 240 DMIPS @ 120 MHz |
| Max Operating Frequency | 120 MHz system clock (ICLK); enables real-time deterministic control loops |
| Flash Memory | 2 MB code flash with dual-bank structure - allows background programming and safe bank-swapping during runtime |
| SRAM | 640 KB total: 256 KB main RAM + 384 KB expansion RAM, all zero-wait-state at 120 MHz |
| Analog Peripherals | Two 12-bit A/D converters (8 + 21 channels), 2-channel 12-bit D/A, on-die temperature sensor (±1°C) |
| Connectivity | Ethernet MAC + PHY, 2× CAN (32 mailboxes/channel), 3× RSPI, 1× QSPI, 3× I²C (1 Mbps), 13× SCI, SDHI/SDSI/MMCIF |
| Security & Safety | AES-128/192/256, TSIP, MPU (8 regions), Trusted Memory (TM), CRC calculator, IWDT with window function, register write protection |
Pinout & Package
Package: PLQP0176KB-A - 176-pin Low-Profile Quad Flat Package (LFBGA), 24 × 24 mm, 0.5 mm pitch, RoHS-compliant, rated for –40°C to +105°C (G-version).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Power supply inputs | Separate digital (VCC) and analog (AVCC0/AVCC1) rails ensure noise isolation for ADC/DAC operation |
| RES# | Active-low reset input | Asynchronous hardware reset; initiates full system initialization sequence |
| CLKIN / CLKOUT | External crystal oscillator interface | Supports 8–24 MHz crystal; enables precise clock source for Ethernet and USB timing |
| ETH_MDC / ETH_MDIO | MDIO management interface | IEEE 802.3-compliant PHY configuration and status monitoring |
| TXD0 / RXD0 / RTS0 / CTS0 | SCI0 UART signals | Full-duplex asynchronous communication with hardware flow control for debug or host interface |
| CRX0 / CTX0 / CRX1 / CTX1 | CAN transceiver I/O | Differential bus interface for ISO 11898-1 compliant CAN FD-capable physical layer (note: R5F565N4AGFB#10 supports standard CAN only) |
| SD0DAT0–3 / SD0CMD / SD0CLK | SD host interface signals | 4-bit SD bus supporting high-speed mode (25 MB/s) per SD Spec v3.01 |
Key Features
| Feature | Design Value |
|---|---|
| Dual-bank flash architecture | Enables seamless firmware updates without halting real-time operation - critical for industrial uptime requirements |
| Integrated Ethernet PHY | Eliminates need for external PHY IC; reduces BOM count and PCB area while maintaining IEEE 802.3u MII/RMII compliance |
| GLCDC + DRW2D graphics engine | Hardware-accelerated LCD rendering with 3-plane overlay and 2D vector/bit-blit operations - offloads CPU in HMI applications |
| IEC 60730 Class B support | Includes oscillation-stop detection, CRC calculator, IWDT with windowing, self-diagnostic A/D, and register lock - simplifies functional safety certification |
| Event Link Controller (ELC) | 83 internal event signals routed without CPU intervention - enables deterministic low-latency peripheral coordination (e.g., timer-triggered ADC capture) |
Applications
| Industrial Gateway | Secure Edge Node |
|---|---|
Use Scenario: Aggregating Modbus RTU, CAN, and serial fieldbus data into encrypted TLS-secured MQTT packets for cloud upload via Ethernet. IC Role / Device Role / Timing Role: Central protocol translator and security enforcer - performs real-time CAN message filtering, AES-256 encryption, and Ethernet frame assembly. Use Value: Dual CAN channels (32 mailboxes each) enable concurrent multi-bus monitoring; hardware AES reduces encryption latency by >90% vs. software-only implementation. |
Use Scenario: Tamper-resistant sensor node in smart metering, logging temperature, voltage, and current with cryptographic signing before local SD storage and periodic Ethernet upload. IC Role / Device Role / Timing Role: Trusted execution environment - uses Trusted Memory (TM) to isolate firmware, TSIP for key management, and register write protection to prevent runtime corruption. Use Value: On-die temperature sensor (±1°C) and 12-bit dual A/D units allow calibrated metrology-grade measurements without external signal conditioning. |
| HMI Controller | Networked PLC Module |
Use Scenario: Driving 480×272 RGB TFT display with touch overlay in factory-floor operator panel, running real-time UI logic and local alarm handling. IC Role / Device Role / Timing Role: Graphics subsystem controller - manages frame buffer via GLCDC, accelerates UI drawing via DRW2D, and handles touch input via parallel data capture unit (PDC). Use Value: 640 KB zero-wait-state SRAM hosts full frame buffer and UI assets; 2D engine supports rotation/scaling without CPU load - maintains >60 FPS UI responsiveness. |
Use Scenario: Compact DIN-rail mounted PLC module executing ladder logic, communicating over EtherNet/IP and CANopen, with local I/O expansion via SDIO peripherals. IC Role / Device Role / Timing Role: Deterministic real-time controller - leverages fast interrupt response (<100 ns), MTU3 PWM outputs for servo drive control, and ELC for jitter-free I/O synchronization. Use Value: 25 extended-function timers (TPUa, MTU3a, CMTW) provide precise PWM generation (complementary, dead-time configurable) and encoder counting for motion control loops. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F565NEDFP#30 | Same RX65N Group, 144-pin LQFP package (PLQP0144KA-B), 2 MB flash, but only 256 KB SRAM and no integrated Ethernet PHY | Lacks Ethernet PHY and GLCDC - suitable for cost-sensitive CAN/serial gateway where external PHY or display controller is acceptable | Select when board space permits larger LQFP footprint and Ethernet connectivity is implemented externally |
| R5F566TEADFP#30 | RX66T Group part: 160 MHz CPU, 2 MB flash, 384 KB SRAM, no Ethernet PHY, adds motor control timers (IMIA/IMIB) and enhanced MTU3 | Optimized for servo/inverter control with advanced PWM and encoder interfaces - lacks SDHI, GLCDC, and TSIP | Prefer for high-performance motor drives requiring 160 MHz deterministic timing and advanced PWM dead-time compensation |
Compared with R5F565N4AGFB#10, the R5F565NEDFP#30 trades Ethernet PHY integration and graphics capability for lower-cost packaging and simpler layout, while the R5F566TEADFP#30 shifts focus toward motor control with higher clock speed and specialized timers but removes key HMI and secure networking features.
Availability
R5F565N4AGFB#10 is available at Aetrix Electronics and suitable for industrial gateways, secure edge nodes, HMI controllers, and networked PLC modules requiring stable component supply, long-term lifecycle assurance, and automotive-grade reliability under extended temperature conditions.
Supply support for R5F565N4AGFB#10 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for industrial, automotive, and enterprise applications.
The RX65N Group - including R5F565N4AGFB#10 - was designed for secure, connected industrial edge devices requiring integrated Ethernet, rich graphics, functional safety, and robust real-time performance in harsh environments.
FAQ
What is the operating temperature range for the R5F565N4AGFB#10?
The R5F565N4AGFB#10 is rated for –40°C to +105°C (G-version), making it suitable for industrial environments with wide thermal variation. This rating applies to the full functional specification including Ethernet MAC, CAN, and GLCDC operation - confirmed in Renesas datasheet R01DS0276EJ0240 Section 1.1 and Package Specification PLQP0176KB-A.
Does the R5F565N4AGFB#10 include an integrated Ethernet PHY?
Yes, the R5F565N4AGFB#10 integrates a full IEEE 802.3u-compliant Ethernet PHY supporting both MII and RMII interfaces. This eliminates the need for an external PHY IC and is explicitly documented in the "Communication function" section of the R01DS0276EJ0240 datasheet, Page 7.
How much SRAM does the R5F565N4AGFB#10 provide, and is it zero-wait-state?
The R5F565N4AGFB#10 provides 640 KB of on-chip SRAM: 256 KB main RAM plus 384 KB expansion RAM. All 640 KB operate at zero wait states up to 120 MHz - verified in Table 1.1 (Page 3) and Section 1.1.2 "RAM" of the R01DS0276EJ0240 datasheet.
Is the R5F565N4AGFB#10 supported for IEC 60730 Class B compliance?
Yes, the R5F565N4AGFB#10 includes dedicated hardware features for IEC 60730 Class B: oscillation-stop detection, CRC calculator (CRCA), independent watchdog timer (IWDT) with window function, self-diagnostic A/D, and register write protection - all listed in the "Useful functions for IEC60730 compliance" section (Page 1) of R01DS0276EJ0240.
What package type and pin count does the R5F565N4AGFB#10 use?
The R5F565N4AGFB#10 uses the PLQP0176KB-A package: a 176-pin Low-Profile Quad Flat Package (LFBGA) with 24 × 24 mm body size and 0.5 mm pitch. This is specified in the "Package Information" section of the R01DS0276EJ0240 datasheet (Page 187) and Renesas ordering information.
R5F565N4AGFB#10 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 144-LQFP
- Series:
- RX65N
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv2
- Core Size:
- 32-Bit
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, QSPI, SCI, SPI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 111
- Program Memory Size:
- 512KB (512K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 256K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 29x12b; D/A 2x12b
- Oscillator Type:
- External
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F565N4AGFB#10 FAQ
1.How can I place an order for R5F565N4AGFB#10 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F565N4AGFB#10 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F565N4AGFB#10 reliable?
The price and inventory of R5F565N4AGFB#10 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F565N4AGFB#10 is usually 5 days.
3.What payment methods are accepted for R5F565N4AGFB#10?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F565N4AGFB#10 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F565N4AGFB#10?
R5F565N4AGFB#10 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F565N4AGFB#10 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F565N4AGFB#10?
For technical support, including R5F565N4AGFB#10 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F565N4AGFB#10 requirements.
6.How does Aetrix verify that R5F565N4AGFB#10 is sourced from the original manufacturer or authorized distributors?
All R5F565N4AGFB#10 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F565N4AGFB#10 meets industry standards.
7.What is the process for return or replacement of R5F565N4AGFB#10?
All R5F565N4AGFB#10 units undergo pre-shipment inspection (PSI). If there is an issue with R5F565N4AGFB#10, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F565N4AGFB#10 part is unused and in its original packaging.
Return procedure for R5F565N4AGFB#10:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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