Renesas R5F565N4AGFP#10
- Part No.:
- R5F565N4AGFP#10
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 100-LQFP
- Datasheet:
-
R5F565N4AGFP#10.pdf
- Description:
- IC MCU 32BIT 512KB FLSH 100LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:2,649
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Product details
Overview
R5F565N4AGFP#10 from Renesas is a 120-MHz 32-bit RXv2 microcontroller with single-precision IEEE-754 FPU, 240 DMIPS performance, 2 MB on-chip code flash (dual-bank), 640 KB SRAM, and integrated Ethernet MAC, CAN, SD host/slave, QSPI, and GLCDC for embedded HMI and industrial connectivity applications.
For engineers reviewing the R5F565N4AGFP#10 datasheet, R5F565N4AGFP#10 pinout, R5F565N4AGFP#10 application, or R5F565N4AGFP#10 equivalent, this MCU delivers deterministic real-time control with IEC60730 safety support, hardware encryption (AES-128/192/256 + TSIP), and low-power operation across –40°C to +105°C.
Technical Context
The R5F565N4AGFP#10 implements the RXv2 CPU core with 5-stage CISC Harvard pipeline, variable-length instructions, and MPU-based memory protection. It integrates dual-clock domain peripherals: PCLKA-synchronized modules (ETHERC, EDMAC, AES, GLCDC, DRW2D) run up to 120 MHz, while PCLKB-synchronized modules (S12AD, TMR, CMT) operate up to 60 MHz.
Its clock system combines external crystal (8–24 MHz), internal HOCO (16/18/20 MHz), LOCO (240 kHz), and PLL for flexible frequency synthesis. The device supports four low-power modes, RTC battery backup via VBATT, and independent watchdog (IWDT) with windowed refresh timing - all validated for IEC60730 Class B compliance.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit CISC Harvard architecture with 5-stage pipeline and 240 DMIPS @ 120 MHz |
| Flash Memory | 2 MB code flash with dual-bank structure enabling background programming and safe firmware updates |
| SRAM | 640 KB on-chip SRAM (256 KB main + 384 KB expansion), zero-wait-state access at 120 MHz |
| Analog Peripherals | Two 12-bit A/D converters (8 + 21 channels), two 12-bit D/A channels, on-die temperature sensor (±1°C) |
| Connectivity | Ethernet MAC (10/100 Mbps MII/RMII), CAN v2.0B (2 channels, 32 mailboxes each), USB 2.0 FS host/function/OTG |
| Security & Safety | AES-128/192/256 + Trusted Secure IP (TSIP), MPU, CRC calculator (8/32-bit), register write protection, self-diagnostic A/D |
| Package & Temp | 176-pin LFBGA (PLQP0176KB-A, 24 × 24 mm, 0.5 mm pitch), industrial grade (–40°C to +105°C) |
Pinout & Package
Package: PLQP0176KB-A - 176-pin Low-Profile Quad Flat Package (LFBGA), 24 mm × 24 mm, 0.5 mm pitch, RoHS-compliant, G-version (–40°C to +105°C).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Power supply inputs | Separate analog/digital domains; AVCC0/AVCC1 power S12AD units; VCC powers digital logic and I/O |
| VBATT | Battery backup supply | Enables RTC operation during main power loss; requires external coin cell or supercapacitor |
| RES# | Active-low reset input | Hardware reset assertion; synchronous release after power stabilization and internal POR delay |
| CLKIN / CLKOUT | External crystal interface | Supports 8–24 MHz crystal/resonator; CLKOUT provides buffered output for trace/debug clocking |
| ETXD0–7 / ERXD0–7 | Ethernet PHY data bus | 8-bit MII interface signals; require external PHY or RMII transceiver depending on configuration |
| TXD0 / RXD0 | SCI0 serial interface | Asynchronous UART mode default; configurable as SPI/I²C/smart card; supports LIN via SCIh |
| PE0–PE15 | General-purpose I/O port E | 5-V tolerant, open-drain capable, pull-up configurable; used for ELC event linking and PWM output control |
Key Features
| Feature | Design Value |
|---|---|
| Dual-bank flash architecture | Enables seamless firmware updates without halting execution - critical for OTA and fail-safe field upgrades |
| Integrated GLCDC + DRW2D | Hardware-accelerated 2D graphics rendering and LCD panel control eliminates need for external display controller |
| SDHI/SDSI + MMCIF | Single-chip support for SD memory cards, SDIO peripherals (Wi-Fi/BT modules), and eMMC storage - no external bridge IC required |
| IEC60730 Class B ready | Includes oscillation-stop detection, CRC calculator, IWDT windowing, A/D self-test, and register write protection for certified safety firmware |
| Event Link Controller (ELC) | 83 internal event sources routed without CPU intervention - reduces latency and ISR overhead in time-critical control loops |
Applications
| Industrial HMI Panel | Smart Gateway Device |
|---|---|
Use Scenario: Touch-enabled factory operator interface with local graphics rendering and remote diagnostics over Ethernet. IC Role / Device Role / Timing Role: Main application processor executing RTOS, driving TFT-LCD via GLCDC, managing touch input, and handling Modbus TCP over Ethernet MAC. Use Value: On-chip DRW2D accelerates UI redraws; dual-bank flash enables secure firmware patching during runtime without service interruption. | Use Scenario: Protocol-convergent edge gateway connecting legacy RS-485 field devices to cloud via cellular/Ethernet. IC Role / Device Role / Timing Role: Central protocol translator running multiple stacks (CAN, Modbus RTU, MQTT), buffering data in 640 KB SRAM, and securing payloads with AES/TSIP. Use Value: Integrated CAN + Ethernet + USB eliminates external transceivers; hardware crypto offloads TLS handshake overhead from application CPU. |
| Medical Data Logger | Building Automation Controller |
Use Scenario: Battery-backed patient monitor logging vital signs with tamper-proof audit trail and wireless upload. IC Role / Device Role / Timing Role: Real-time acquisition controller using S12AD with self-diagnostic, RTC timestamping, and encrypted SD card storage via SDHI. Use Value: VBATT-powered RTC maintains accurate timestamps during main power loss; AES-256 encrypts stored health records per HIPAA requirements. | Use Scenario: HVAC controller managing zone sensors, actuators, and BACnet/IP communication in commercial buildings. IC Role / Device Role / Timing Role: Deterministic real-time scheduler coordinating 12-bit A/D sampling, PWM fan control, CAN bus supervision, and Ethernet-based BACnet stack. Use Value: MTU3 complementary PWM outputs drive 3-phase inverters with programmable dead time; ELC synchronizes sensor reads with actuator updates. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F565NEDFP#30 | Same RX65N Group, identical 176-pin LFBGA package, but with 1.5 MB flash and 256 KB SRAM (not 640 KB) | Suitable for cost-sensitive designs where full 2 MB flash and extended RAM are unnecessary | Select when firmware size < 1.5 MB and graphics/display buffer requirements are modest |
| R5F566NEDFP#30 | RX66N Group successor: higher 160 MHz CPU, enhanced TSIP-Lite, larger peripheral set, same 176-pin footprint | Targets next-gen designs requiring higher throughput, advanced security, or future-proof scalability | Choose for new designs prioritizing longevity, higher performance, or extended safety certification paths |
Compared with R5F565N4AGFP#10, R5F565NEDFP#30 offers reduced memory resources at lower cost, while R5F566NEDFP#30 delivers architectural upgrades including faster CPU, stronger crypto acceleration, and expanded peripheral bandwidth - making it ideal for forward-looking industrial platforms.
Availability
R5F565N4AGFP#10 is available at Aetrix Electronics and suitable for industrial HMI panels, smart gateways, medical data loggers, and building automation controllers requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for R5F565N4AGFP#10 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.
The RX65N Group - including R5F565N4AGFP#10 - was designed for high-integration industrial human-machine interfaces and networked edge devices requiring real-time responsiveness, functional safety, and rich multimedia capability.
FAQ
What is the maximum operating frequency and CPU architecture of the R5F565N4AGFP#10?
The R5F565N4AGFP#10 operates at a maximum frequency of 120 MHz using the 32-bit RXv2 CPU core. This core features a 5-stage CISC Harvard pipeline, variable-length instructions, single-cycle 32×32 multiplier, and IEEE-754-compliant floating-point unit delivering 240 DMIPS. Its architecture supports memory protection (MPU), fast interrupt response, and JTAG/FINE debugging interfaces - all confirmed in Renesas document R01DS0276EJ0240.
Does the R5F565N4AGFP#10 support hardware encryption and functional safety standards?
Yes, the R5F565N4AGFP#10 integrates AES-128/192/256 engines and Trusted Secure IP (TSIP) for cryptographic acceleration. It also includes IEC60730 Class B compliance features: oscillation-stop detection, CRC calculator (8/32-bit), independent watchdog timer (IWDT) with windowing, A/D self-diagnostic, and register write protection - all documented in the RX65N Group datasheet R01DS0276EJ0240.
What are the memory resources available on the R5F565N4AGFP#10?
The R5F565N4AGFP#10 includes 2 MB of on-chip code flash memory with dual-bank architecture for background programming, 640 KB of SRAM (256 KB main + 384 KB expansion), and 32 KB of reprogrammable data flash rated for 100,000 erase/write cycles. It also provides 8 KB of standby RAM backed by VBATT - all verified in Section 1.1 of R01DS0276EJ0240 Rev.2.40.
Which communication interfaces does the R5F565N4AGFP#10 integrate?
The R5F565N4AGFP#10 integrates Ethernet MAC (10/100 Mbps MII/RMII), CAN v2.0B (2 channels, 32 mailboxes each), USB 2.0 FS host/function/OTG, SD host/slave (SDHI/SDSI), MMCIF, QSPI, three RSPI channels, three I²C interfaces (up to 1 Mbps), and up to 13 SCI channels supporting UART/SPI/I²C/LIN protocols - as specified in Table 1.1 and Section 1. Overview of R01DS0276EJ0240.
What is the package type and temperature range for the R5F565N4AGFP#10?
The R5F565N4AGFP#10 uses the PLQP0176KB-A package: a 176-pin LFBGA with 24 mm × 24 mm body and 0.5 mm pitch. It is rated for the industrial temperature range of –40°C to +105°C (G-version), as defined in the "Ordering Information" section and package drawings of R01DS0276EJ0240 Rev.2.40.
R5F565N4AGFP#10 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 100-LQFP
- Series:
- RX65N
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv2
- Core Size:
- 32-Bit
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, QSPI, SCI, SPI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 78
- Program Memory Size:
- 512KB (512K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 256K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 22x12b; D/A 1x12b
- Oscillator Type:
- External
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F565N4AGFP#10 FAQ
1.How can I place an order for R5F565N4AGFP#10 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F565N4AGFP#10 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F565N4AGFP#10 reliable?
The price and inventory of R5F565N4AGFP#10 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F565N4AGFP#10 is usually 5 days.
3.What payment methods are accepted for R5F565N4AGFP#10?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F565N4AGFP#10 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F565N4AGFP#10?
R5F565N4AGFP#10 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F565N4AGFP#10 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F565N4AGFP#10?
For technical support, including R5F565N4AGFP#10 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F565N4AGFP#10 requirements.
6.How does Aetrix verify that R5F565N4AGFP#10 is sourced from the original manufacturer or authorized distributors?
All R5F565N4AGFP#10 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F565N4AGFP#10 meets industry standards.
7.What is the process for return or replacement of R5F565N4AGFP#10?
All R5F565N4AGFP#10 units undergo pre-shipment inspection (PSI). If there is an issue with R5F565N4AGFP#10, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F565N4AGFP#10 part is unused and in its original packaging.
Return procedure for R5F565N4AGFP#10:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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